Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM
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Published Version
Date
2009-02
Authors
Ye, Zhipeng
Kennedy, Michael Peter
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Publisher
IEEE
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Abstract
In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs.
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Keywords
Digital delta-sigma modulators , Error masking , Reduced complexity
Citation
Ye, Z., Kennedy, M.P., 2009. Hardware reduction in digital delta-sigma modulators via error masking - part II: Sq-DDSM. IEEE Transactions On Circuits and Systems II - Express Briefs, 56 (2), pp.112-116.
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