• Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources 

  Zheng, Hao (University College Cork, 2021-06)

  This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained ...
• Direct air capture (DAC): capturing CO2 from the air – design of a lab-scale PVSA system and the development of a carbon-based adsorbent material for atmospheric CO2 capture 

  Dineen, Cormac P.J. (University College Cork, 2020-05-06)

  Mankind faces huge economic, technological and societal challenges if we are to meet the climate targets set out in the Paris Climate Agreement of limiting global warming to 2°C and avoid the most devastating effects of ...

View more