The role of oxide traps aligned with the semiconductor energy gap in MOS systems

Show simple item record Caruso, Enrico Lin, Jun Monaghan, Scott Cherkaoui, Karim Gity, Farzan Palestri, Pierpaolo Esseni, David Selmi, Luca Hurley, Paul K. 2020-11-09T10:20:40Z 2020-11-09T10:20:40Z 2020-08-31
dc.identifier.citation Caruso, E., Lin, J., Monaghan, S., Cherkaoui, K., Gity, F., Palestri, P., Esseni, D., Selmi, L. and Hurley, P. K. (2020) 'The role of oxide traps aligned with the semiconductor energy gap in MOS systems', IEEE Transactions on Electron Devices, 67(10), pp. 4372-4378. doi: 10.1109/TED.2020.3018095 en
dc.identifier.volume 67 en
dc.identifier.issued 10 en
dc.identifier.startpage 4372 en
dc.identifier.endpage 4378 en
dc.identifier.issn 0018-9383
dc.identifier.doi 10.1109/TED.2020.3018095 en
dc.description.abstract This work demonstrates that when inelastic tunneling between oxide traps and semiconductor bands is considered, the traps with energy aligned to the semiconductor bandgap play a significant role in the frequency dispersion of the capacitance–voltage ( C–V ) and conductance–voltage ( G–V ) characteristics of metal–oxide–semiconductor (MOS) systems. The work also highlights that a nonlocal model for tunneling into interface states is mandatory to reproduce experiments when carrier quantization in the inversion layer is accounted for. A model, including these ingredients, is used to evaluate the energy and depth distribution of oxide traps in a n-In 0.53 Ga 0.47 As/Al 2 O 3 MOS system and is able to accurately fit the C–V frequency dispersion from depletion to weak inversion. The oxide trap distribution determined from the C–V response predicts the corresponding G–V dispersion with frequency. en
dc.description.sponsorship Science Foundation Ireland (12/RC/2278_P2) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.rights © 2020, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject Al2O3 en
dc.subject Defects en
dc.subject InGaAs en
dc.subject Interface traps en
dc.subject Multifrequency en
dc.subject Multiphonon en
dc.subject Nonradiative multiphonon (NMP) en
dc.subject Oxide traps en
dc.subject Quantization en
dc.subject Quantum effects en
dc.subject Spectroscopy en
dc.subject TCAD en
dc.subject Tunneling en
dc.subject Capacitance–voltage (C–V) en
dc.subject Conductance–voltage (G–V) en
dc.title The role of oxide traps aligned with the semiconductor energy gap in MOS systems en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Paul Hurley, Tyndall Micronano Electronics, University College Cork, Cork, Ireland. +353-21-490-3000 Email: en
dc.internal.availability Full text available en 2020-11-09T10:10:43Z
dc.description.version Accepted Version en
dc.internal.rssid 538008058
dc.contributor.funder Horizon 2020 en
dc.contributor.funder Science Foundation Ireland en
dc.description.status Peer reviewed en
dc.identifier.journaltitle IEEE Transactions on Electron Devices en
dc.internal.copyrightchecked Yes
dc.internal.licenseacceptance Yes en
dc.internal.IRISemailaddress en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/871764/EU/Cryogenic 3D Nanoelectronics/SEQUENCE en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/688784/EU/Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies/INSIGHT en
dc.identifier.eissn 1557-9646

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