Hardware design of cryptographic accelerators

Show simple item record

dc.contributor.advisor Marnane, William P. en
dc.contributor.author Baldwin, Brian John
dc.date.accessioned 2013-05-09T15:47:31Z
dc.date.available 2013-05-09T15:47:31Z
dc.date.issued 2013
dc.date.submitted 2013
dc.identifier.citation Baldwin, B.J., 2013. Hardware design of cryptographic accelerators. PhD Thesis, University College Cork. en
dc.identifier.endpage 215
dc.identifier.uri http://hdl.handle.net/10468/1112
dc.description.abstract With the rapid growth of the Internet and digital communications, the volume of sensitive electronic transactions being transferred and stored over and on insecure media has increased dramatically in recent years. The growing demand for cryptographic systems to secure this data, across a multitude of platforms, ranging from large servers to small mobile devices and smart cards, has necessitated research into low cost, flexible and secure solutions. As constraints on architectures such as area, speed and power become key factors in choosing a cryptosystem, methods for speeding up the development and evaluation process are necessary. This thesis investigates flexible hardware architectures for the main components of a cryptographic system. Dedicated hardware accelerators can provide significant performance improvements when compared to implementations on general purpose processors. Each of the designs proposed are analysed in terms of speed, area, power, energy and efficiency. Field Programmable Gate Arrays (FPGAs) are chosen as the development platform due to their fast development time and reconfigurable nature. Firstly, a reconfigurable architecture for performing elliptic curve point scalar multiplication on an FPGA is presented. Elliptic curve cryptography is one such method to secure data, offering similar security levels to traditional systems, such as RSA, but with smaller key sizes, translating into lower memory and bandwidth requirements. The architecture is implemented using different underlying algorithms and coordinates for dedicated Double-and-Add algorithms, twisted Edwards algorithms and SPA secure algorithms, and its power consumption and energy on an FPGA measured. Hardware implementation results for these new algorithms are compared against their software counterparts and the best choices for minimum area-time and area-energy circuits are then identified and examined for larger key and field sizes. Secondly, implementation methods for another component of a cryptographic system, namely hash functions, developed in the recently concluded SHA-3 hash competition are presented. Various designs from the three rounds of the NIST run competition are implemented on FPGA along with an interface to allow fair comparison of the different hash functions when operating in a standardised and constrained environment. Different methods of implementation for the designs and their subsequent performance is examined in terms of throughput, area and energy costs using various constraint metrics. Comparing many different implementation methods and algorithms is nontrivial. Another aim of this thesis is the development of generic interfaces used both to reduce implementation and test time and also to enable fair baseline comparisons of different algorithms when operating in a standardised and constrained environment. Finally, a hardware-software co-design cryptographic architecture is presented. This architecture is capable of supporting multiple types of cryptographic algorithms and is described through an application for performing public key cryptography, namely the Elliptic Curve Digital Signature Algorithm (ECDSA). This architecture makes use of the elliptic curve architecture and the hash functions described previously. These components, along with a random number generator, provide hardware acceleration for a Microblaze based cryptographic system. The trade-off in terms of performance for flexibility is discussed using dedicated software, and hardware-software co-design implementations of the elliptic curve point scalar multiplication block. Results are then presented in terms of the overall cryptographic system. en
dc.description.sponsorship Science Foundation Ireland (06/MI/006) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2013. Brian J. Baldwin en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject Cryptography en
dc.subject Reconfigurable hardware en
dc.subject Elliptic curve cryptography en
dc.subject Hash functions en
dc.subject Field programmable gate arrays (FPGAs) en
dc.subject.lcsh Data encryption (Computer science). en
dc.title Hardware design of cryptographic accelerators en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PHD (Engineering) en
dc.internal.availability Full text available en
dc.check.info No embargo required en
dc.description.version Accepted Version
dc.contributor.funder Science Foundation Ireland en
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.check.type No Embargo Required
dc.check.reason No embargo required en
dc.check.opt-out Not applicable en
dc.thesis.opt-out false *
dc.check.embargoformat Not applicable en
ucc.workflow.supervisor l.marnane@ucc.ie *

Files in this item

This item appears in the following Collection(s)

Show simple item record

© 2013. Brian J. Baldwin Except where otherwise noted, this item's license is described as © 2013. Brian J. Baldwin
This website uses cookies. By using this website, you consent to the use of cookies in accordance with the UCC Privacy and Cookies Statement. For more information about cookies and how you can disable them, visit our Privacy and Cookies statement