Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources

Loading...
Thumbnail Image
Files
Date
2021-06
Authors
Zheng, Hao
Journal Title
Journal ISSN
Volume Title
Publisher
University College Cork
Published Version
Research Projects
Organizational Units
Journal Issue
Abstract
This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW.
Description
Keywords
Mixed signal compensation , DPLL clock sources , Sampling errors in ADCs
Citation
Zheng, H. 2021. Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources. MRes Thesis, University College Cork.