A study of silicon and germanium junctionless transistors

Show simple item record

dc.contributor.advisor Colinge, Jean-Pierre en
dc.contributor.advisor Duffy, Ray en
dc.contributor.author Yu, Ran
dc.date.accessioned 2013-12-18T12:49:06Z
dc.date.available 2013-12-18T12:49:06Z
dc.date.issued 2013
dc.date.submitted 2013
dc.identifier.citation Yu, R. 2013. A study of silicon and germanium junctionless transistors. PhD Thesis, University College Cork. en
dc.identifier.endpage 151
dc.identifier.uri http://hdl.handle.net/10468/1283
dc.description.abstract Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V. en
dc.description.sponsorship European Commission (FP7) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2013, Ran Yu. en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject Germanium junctionless nanowire transistor en
dc.subject.lcsh Silicon en
dc.subject.lcsh Germanium en
dc.subject.lcsh Transistors en
dc.title A study of silicon and germanium junctionless transistors en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PHD (Engineering) en
dc.internal.availability Full text available en
dc.check.info No embargo required en
dc.description.version Accepted Version
dc.contributor.funder Science Foundation Ireland en
dc.contributor.funder European Commission en
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.internal.school Tyndall National Institute en
dc.check.type No Embargo Required
dc.check.reason No embargo required en
dc.check.opt-out Not applicable en
dc.thesis.opt-out false *
dc.check.embargoformat Not applicable en
ucc.workflow.supervisor ray.duffy@tyndall.ie *
dc.internal.conferring Autumn Conferring 2013 en


Files in this item

This item appears in the following Collection(s)

Show simple item record

© 2013, Ran Yu. Except where otherwise noted, this item's license is described as © 2013, Ran Yu.
This website uses cookies. By using this website, you consent to the use of cookies in accordance with the UCC Privacy and Cookies Statement. For more information about cookies and how you can disable them, visit our Privacy and Cookies statement