Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM

Show simple item record

dc.contributor.author Ye, Zhipeng
dc.contributor.author Kennedy, Michael Peter
dc.date.accessioned 2010-03-26T17:23:56Z
dc.date.available 2010-03-26T17:23:56Z
dc.date.issued 2009-02
dc.identifier.citation Ye, Z., Kennedy, M.P., 2009. Hardware reduction in digital delta-sigma modulators via error masking - part II: Sq-DDSM. IEEE Transactions On Circuits and Systems II - Express Briefs, 56 (2), pp.112-116. en
dc.identifier.volume 56 en
dc.identifier.issued 2 en
dc.identifier.startpage 112 en
dc.identifier.endpage 116 en
dc.identifier.issn 1549-7747
dc.identifier.uri http://hdl.handle.net/10468/131
dc.identifier.doi 10.1109/TCSII.2008.2010188
dc.description.abstract In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs. en
dc.description.sponsorship Science Foundation Ireland (Grant 02/IN.1/I45, Grant 08/IN.1/I1854); Irish Research Council for Science, Engineering and Technology (Grant SC/2002/409). en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher IEEE en
dc.rights ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. en
dc.subject Digital delta-sigma modulators en
dc.subject Error masking en
dc.subject Reduced complexity en
dc.subject.lcsh Digital modulation en
dc.title Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Michael Peter Kennedy, Vice President Research, University College Cork, Cork, Ireland. Email: peter.kennedy@ucc.ie en
dc.internal.availability Full text available en
dc.date.updated 2010-03-26T16:16:55Z
dc.description.version Published Version en
dc.internal.rssid 721501
dc.internal.wokid 177648542
dc.contributor.funder Science Foundation Ireland en
dc.contributor.funder Irish Research Council for Science Engineering and Technology
dc.description.status Peer reviewed en
dc.identifier.journaltitle IEEE Transactions On Circuits and Systems II - Express Briefs en
dc.internal.IRISemailaddress peter.kennedy@ucc.ie en


Files in this item

This item appears in the following Collection(s)

Show simple item record

This website uses cookies. By using this website, you consent to the use of cookies in accordance with the UCC Privacy and Cookies Statement. For more information about cookies and how you can disable them, visit our Privacy and Cookies statement