Cryptographic coprocessors for embedded systems

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dc.contributor.advisor Marnane, William P. en
dc.contributor.author Hamilton, Mark
dc.date.accessioned 2015-01-26T10:09:30Z
dc.date.available 2015-01-26T10:09:30Z
dc.date.issued 2014
dc.date.submitted 2014
dc.identifier.citation Hamilton, M. 2014. Cryptographic coprocessors for embedded systems. PhD Thesis, University College Cork. en
dc.identifier.endpage 174
dc.identifier.uri http://hdl.handle.net/10468/1770
dc.description.abstract In the field of embedded systems design, coprocessors play an important role as a component to increase performance. Many embedded systems are built around a small General Purpose Processor (GPP). If the GPP cannot meet the performance requirements for a certain operation, a coprocessor can be included in the design. The GPP can then offload the computationally intensive operation to the coprocessor; thus increasing the performance of the overall system. A common application of coprocessors is the acceleration of cryptographic algorithms. The work presented in this thesis discusses coprocessor architectures for various cryptographic algorithms that are found in many cryptographic protocols. Their performance is then analysed on a Field Programmable Gate Array (FPGA) platform. Firstly, the acceleration of Elliptic Curve Cryptography (ECC) algorithms is investigated through the use of instruction set extension of a GPP. The performance of these algorithms in a full hardware implementation is then investigated, and an architecture for the acceleration the ECC based digital signature algorithm is developed. Hash functions are also an important component of a cryptographic system. The FPGA implementation of recent hash function designs from the SHA-3 competition are discussed and a fair comparison methodology for hash functions presented. Many cryptographic protocols involve the generation of random data, for keys or nonces. This requires a True Random Number Generator (TRNG) to be present in the system. Various TRNG designs are discussed and a secure implementation, including post-processing and failure detection, is introduced. Finally, a coprocessor for the acceleration of operations at the protocol level will be discussed, where, a novel aspect of the design is the secure method in which private-key data is handled en
dc.description.sponsorship Science Foundation Ireland (SFI Grant 06/MI/006) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2014, Mark Hamilton en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject FPGA en
dc.subject Elliptic curve cryptography (ECC) en
dc.subject TRNG en
dc.subject Hash functions en
dc.subject AES en
dc.subject SSL/TLS en
dc.subject Cryptography en
dc.title Cryptographic coprocessors for embedded systems en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PHD (Engineering) en
dc.internal.availability Full text available en
dc.check.info No embargo required en
dc.description.version Accepted Version
dc.contributor.funder Science Foundation Ireland en
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.check.type No Embargo Required
dc.check.reason No embargo required en
dc.check.opt-out Not applicable en
dc.thesis.opt-out false
dc.check.embargoformat Not applicable en
ucc.workflow.supervisor l.marnane@ucc.ie
dc.internal.conferring Summer Conferring 2014


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© 2014, Mark Hamilton Except where otherwise noted, this item's license is described as © 2014, Mark Hamilton
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