Hardware processors for pairing-based cryptography

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dc.contributor.advisor Murphy, Colin en
dc.contributor.author Ronan, Robert
dc.date.accessioned 2016-11-18T11:32:55Z
dc.date.available 2016-11-18T11:32:55Z
dc.date.issued 2016
dc.date.submitted 2016
dc.identifier.citation Ronan, R. 2016. Hardware processors for pairing-based cryptography. PhD Thesis, University College Cork. en
dc.identifier.endpage 265 en
dc.identifier.uri http://hdl.handle.net/10468/3291
dc.description.abstract Bilinear pairings can be used to construct cryptographic systems with very desirable properties. A pairing performs a mapping on members of groups on elliptic and genus 2 hyperelliptic curves to an extension of the finite field on which the curves are defined. The finite fields must, however, be large to ensure adequate security. The complicated group structure of the curves and the expensive field operations result in time consuming computations that are an impediment to the practicality of pairing-based systems. The Tate pairing can be computed efficiently using the ɳT method. Hardware architectures can be used to accelerate the required operations by exploiting the parallelism inherent to the algorithmic and finite field calculations. The Tate pairing can be performed on elliptic curves of characteristic 2 and 3 and on genus 2 hyperelliptic curves of characteristic 2. Curve selection is dependent on several factors including desired computational speed, the area constraints of the target device and the required security level. In this thesis, custom hardware processors for the acceleration of the Tate pairing are presented and implemented on an FPGA. The underlying hardware architectures are designed with care to exploit available parallelism while ensuring resource efficiency. The characteristic 2 elliptic curve processor contains novel units that return a pairing result in a very low number of clock cycles. Despite the more complicated computational algorithm, the speed of the genus 2 processor is comparable. Pairing computation on each of these curves can be appealing in applications with various attributes. A flexible processor that can perform pairing computation on elliptic curves of characteristic 2 and 3 has also been designed. An integrated hardware/software design and verification environment has been developed. This system automates the procedures required for robust processor creation and enables the rapid provision of solutions for a wide range of cryptographic applications. en
dc.format.mimetype application/pdf en
dc.language English en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2016, Robert Ronan. en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject Cryptography en
dc.subject Hardware en
dc.subject Identity based encryption en
dc.subject Software en
dc.subject Bilinear pairings en
dc.subject Elliptic hyperelliptic curves en
dc.subject Automation of design and verification en
dc.title Hardware processors for pairing-based cryptography en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PHD (Engineering) en
dc.internal.availability Full text available en
dc.check.info No embargo required en
dc.description.version Accepted Version
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.check.type No Embargo Required
dc.check.reason No embargo required en
dc.check.opt-out Not applicable en
dc.thesis.opt-out false
dc.check.embargoformat Not applicable en
ucc.workflow.supervisor cmurphy@rennes.ucc.ie
dc.internal.conferring Autumn 2016 en


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