Analysis and design of low phase noise CMOS oscillator circuit topologies

Show simple item record

dc.contributor.advisor Pepe, Domenico en
dc.contributor.advisor Zito, Domenico en
dc.contributor.author Chlis, Ilias
dc.date.accessioned 2017-06-22T10:22:06Z
dc.date.issued 2016
dc.date.submitted 2016
dc.identifier.citation Chlis, I. 2016. Analysis and design of low phase noise CMOS oscillator circuit topologies. PhD Thesis, University College Cork. en
dc.identifier.endpage 131 en
dc.identifier.uri http://hdl.handle.net/10468/4146
dc.description.abstract The research activity carried out during the PhD is focused on the study, analysis and design of millimeter-wave integrated oscillator circuits for high-speed wireless communications. In Chapter 1 comparative analyses of phase noise (PN) in Hartley, Colpitts and commonsource cross-coupled differential pair LC oscillator topologies are carried out under common conditions in 28 nm CMOS technology. The impulse sensitivity function (ISF) is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity. Moreover, the analyses show that there is no superior oscillator topology in the absolute sense, but that the identification of the best circuit topology with respect to phase noise is strictly related to the operating frequency range. In Chapter 2 comparative phase noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the impulse sensitivity function show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Chapter 3 reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10 and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Chapter 4 reports the analyses of three techniques for phase noise reduction in the CMOS Colpitts oscillator circuit topology. Namely, the three techniques are: inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28 nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter, show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that, with respect to the reference values obtained in Chapter 2, the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB and 17 dB at a 1 MHz frequency offset for the oscillation frequencies of 10 GHz and 100 GHz respectively. Chapter 5 reports the analyses of the three techniques discussed in Chapter 4, applied to the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. As in the case of the Colpitts topology, the results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter, show the existence of an optimum bias current density for minimum phase noise. Overall, wih respect to the reference values obtained in Chapter 2, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 17 dB and 16 dB at a 1 MHz frequency offset for the oscillation frequencies of 10 GHz and 100 GHz respectively, with respect to the traditional Hartley topology. Finally, Chapter 6 reports the design of an advanced solution, adopting the techniques discussed in Chapters 4 and 5. The voltage-controlled oscillator (VCO) topology can be tuned from 58.1 GHz to 63.3 GHz. From periodic steady state (PSS) and periodic noise (Pnoise) SpectreRF simulations the best phase noise performance is observed for f0=63.3 GHz, and amounts to -100.2 dBc/Hz at a 1 MHz frequency offset from the oscillation frequency, for a power consumption of 13.6 mW. This corresponds to a figure of merit (FOM) of 185 dB. en
dc.description.sponsorship Science Foundation Ireland (Grants 11/RFP/ECE3325 & 07/SK/I1258) en
dc.format.mimetype application/pdf en
dc.language English en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2016, Ilias Chlis. en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject Colpitts en
dc.subject Hartley en
dc.subject VCO en
dc.subject Inductive degeneration en
dc.subject Optimum current density en
dc.subject Noise filter en
dc.subject Oscillator analysis en
dc.subject Phase noise en
dc.title Analysis and design of low phase noise CMOS oscillator circuit topologies en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PHD (Engineering) en
dc.internal.availability Full text not available en
dc.check.info Restricted to everyone for five years en
dc.check.date 2022-06-21T10:22:06Z
dc.description.version Accepted Version
dc.contributor.funder Science Foundation Ireland en
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.internal.school Tyndall National Institute en
dc.check.reason This thesis is due for publication or the author is actively seeking to publish this material en
dc.check.opt-out No en
dc.thesis.opt-out false
dc.check.entireThesis Entire Thesis Restricted
dc.check.embargoformat Both hard copy thesis and e-thesis en
ucc.workflow.supervisor d.zito@ucc.ie
dc.internal.conferring Summer 2016 en


Files in this item

Files Size Format View

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record

© 2016, Ilias Chlis. Except where otherwise noted, this item's license is described as © 2016, Ilias Chlis.
This website uses cookies. By using this website, you consent to the use of cookies in accordance with the UCC Privacy and Cookies Statement. For more information about cookies and how you can disable them, visit our Privacy and Cookies statement