Electrical performance of III-V gate-all-around nanowire transistors

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dc.contributor.author Razavi, Pedram
dc.contributor.author Fagas, Gíorgos
dc.date.accessioned 2017-07-28T09:23:23Z
dc.date.available 2017-07-28T09:23:23Z
dc.date.issued 2013
dc.identifier.citation Razavi, P. and Fagas, G. (2013) 'Electrical performance of III-V gate-all-around nanowire transistors', Applied Physics Letters, 103(6), pp. 063506. doi: 10.1063/1.4817997 en
dc.identifier.volume 103
dc.identifier.issued 6
dc.identifier.startpage 1
dc.identifier.endpage 3
dc.identifier.issn 0003-6951
dc.identifier.issn 1077-3118
dc.identifier.uri http://hdl.handle.net/10468/4281
dc.identifier.doi 10.1063/1.4817997
dc.description.abstract The performance of III-V inversion-mode and junctionless nanowire field-effect transistors are investigated using quantum simulations and are compared with those of silicon devices. We show that at ultrascaled dimensions silicon can offer better electrical performance in terms of short-channel effects and drive current than other materials. This is explained simply by suppression of source-drain tunneling due to the higher effective mass, shorter natural length, and the higher density of states in the confined channel. We also confirm that III-V junctionless nanowire transistors are more immune to short-channel effects than conventional inversion-mode III-V nanowire field-effect transistors. (C) 2013 AIP Publishing LLC. en
dc.description.sponsorship Science Foundation Ireland (06/IN.1/I857); European Union project SQWIRE (257111) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher AIP Publishing en
dc.relation.uri http://aip.scitation.org/doi/abs/10.1063/1.4817997
dc.rights © 2013 AIP Publishing LLC..This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Razavi, P. and Fagas, G. (2013) 'Electrical performance of III-V gate-all-around nanowire transistors', Applied Physics Letters, 103(6), pp. 063506 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.4817997 en
dc.subject Field-effect transistors en
dc.subject Compound semiconductors en
dc.subject Silicon nanowires en
dc.subject Soi mosfets en
dc.title Electrical performance of III-V gate-all-around nanowire transistors en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Pedram Razavi, Tyndall National Institute, University College Cork, Cork, Ireland +353 (0)21 2346675, Email: pedram.razavi@tyndall.ie en
dc.internal.availability Full text available en
dc.description.version Published Version en
dc.internal.wokid WOS:000322908300081
dc.contributor.funder Science Foundation Ireland
dc.contributor.funder European Commission
dc.description.status Peer reviewed en
dc.identifier.journaltitle Applied Physics Letters en
dc.internal.IRISemailaddress pedram.razavi@tyndall.ie en
dc.identifier.articleid 63506
dc.relation.project info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/257111/EU/Silicon Quantum Wire Transistors/SQWIRE

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