Low-frequency noise in junctionless multigate transistors

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dc.contributor.author Jang, Doyoung
dc.contributor.author Lee, Jae Woo
dc.contributor.author Lee, Chi-Woo
dc.contributor.author Colinge, Jean-Pierre
dc.contributor.author Montes, Laurent
dc.contributor.author Lee, Jung Il
dc.contributor.author Kim, Gyu Tae
dc.contributor.author Ghibaudo, G.
dc.date.accessioned 2017-07-28T11:04:40Z
dc.date.available 2017-07-28T11:04:40Z
dc.date.issued 2011
dc.identifier.citation Jang, D., Lee, J. W., Lee, C.-W., Colinge, J.-P., Montès, L., Lee, J. I., Kim, G. T. and Ghibaudo, G. (2011) 'Low-frequency noise in junctionless multigate transistors', Applied Physics Letters, 98(13), pp. 133502. doi: 10.1063/1.3569724 en
dc.identifier.volume 98
dc.identifier.issued 13
dc.identifier.startpage 1
dc.identifier.endpage 3
dc.identifier.issn 0003-6951
dc.identifier.issn 1077-3118
dc.identifier.uri http://hdl.handle.net/10468/4324
dc.identifier.doi 10.1063/1.3569724
dc.description.abstract Low-frequency noise in n-type junctionless multigate transistors was investigated. It can be well understood with the carrier number fluctuations whereas the conduction is mainly limited by the bulk expecting Hooge mobility fluctuations. The trapping/release of charge carriers is related not only to the oxide-semiconductor interface but also to the depleted channel. The volume trap density is in the range of 6-30 x 10(16) cm(-3) eV(-1), which is similar to Si-SiO2 bulk transistors and remarkably lower than in high-k transistors. These results show that the noise in nanowire devices might be affected by additional trapping centers. (C) 2011 American Institute of Physics. (doi:10.1063/1.3569724) en
dc.description.sponsorship National Research Foundation of Korea (NRF grant Converging Research Center program, Grant No. 2010K000981, WCU Grant No. R32-2008-000-10082-0, GRL Grant No. M6060500007-06A0500-00710, 2005-2002369); Korea Institute of Science and Technology and Centre National pour la Recherche Scientifique et Technique (CNRS KIST LIA collaboration); Science Foundation Ireland (Grant No. 05/IN/I888) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher AIP Publishing en
dc.relation.uri http://aip.scitation.org/doi/abs/10.1063/1.3569724
dc.rights © 2011 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Jang, D., Lee, J. W., Lee, C.-W., Colinge, J.-P., Montès, L., Lee, J. I., Kim, G. T. and Ghibaudo, G. (2011) 'Low-frequency noise in junctionless multigate transistors', Applied Physics Letters, 98(13), pp. 133502 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3569724 en
dc.subject Field-effect transistors en
dc.subject Excess noise en
dc.subject Mos-transistors en
dc.subject 1/f noise en
dc.subject Devices en
dc.subject Model en
dc.subject Carrier mobility en
dc.subject MOSFETs en
dc.subject Nanowires1/f noise en
dc.subject Oxide surfaces en
dc.title Low-frequency noise in junctionless multigate transistors en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Jean-Pierre Colinge, Tyndall National Institute, University College Cork, Cork, Ireland, Email: jpcolinge@yahoo.com en
dc.internal.availability Full text available en
dc.description.version Published Version en
dc.internal.wokid WOS:000289153600091
dc.contributor.funder National Research Foundation of Korea
dc.contributor.funder Fondation Nanosciences
dc.contributor.funder Science Foundation Ireland
dc.contributor.funder Seventh Framework Programme
dc.contributor.funder Korea Institute of Science and Technology
dc.contributor.funder Centre National pour la Recherche Scientifique et Technique
dc.description.status Peer reviewed en
dc.identifier.journaltitle Applied Physics Letters en
dc.internal.IRISemailaddress jpcolinge@yahoo.com en
dc.identifier.articleid 133502
dc.relation.project info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/216171/EU/Silicon-based nanostructures and nanodevices for long term nanoelectronics applications/NANOSIL
dc.relation.project info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/216373/EU/European platform for low-power applications on Silicon-on-Insulator Technology/EUROSOI+


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