Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing

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dc.contributor.author Lin, Jun
dc.contributor.author Monaghan, Scott
dc.contributor.author Cherkaoui, Karim
dc.contributor.author Povey, Ian M.
dc.contributor.author Sheehan, Brendan
dc.contributor.author Hurley, Paul K.
dc.date.accessioned 2017-09-01T09:06:47Z
dc.date.available 2017-09-01T09:06:47Z
dc.date.issued 2017-05-13
dc.identifier.citation Lin, J., Monaghan, S., Cherkaoui, K., Povey, I. M., Sheehan, B. and Hurley, P. K. (2017) 'Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing', Microelectronic Engineering, 178, pp. 204-208. doi:10.1016/j.mee.2017.05.020 en
dc.identifier.volume 178 en
dc.identifier.startpage 204 en
dc.identifier.endpage 208 en
dc.identifier.issn 0167-9317
dc.identifier.uri http://hdl.handle.net/10468/4601
dc.identifier.doi 10.1016/j.mee.2017.05.020
dc.description.abstract In this work, we investigated the effect of forming gas annealing (FGA, 5% H2/95% N2, 250 °C to 450 °C) on border trap density in high-k/InGaAs metal-oxide-semiconductor (MOS) systems using accumulation frequency dispersion and capacitance-voltage (CV) hysteresis analysis. It is demonstrated that the optimum FGA temperature that reduces the accumulation frequency dispersion is 350 °C for HfO2/n-InGaAs and 450 °C for Al2O3/n-InGaAs MOS system. Volume density of border traps (Nbt) is estimated using the accumulation frequency dispersion based on a distributed model for border traps. It is shown that for HfO2/n-InGaAs MOS system, Nbt is reduced from 9.4 × 1019 cm− 3 eV− 1 before FGA to 6.3 × 1019 cm− 3 eV− 1 following FGA at 350 °C. For the case of Al2O3/n-InGaAs MOS system, Nbt is reduced from 5.7 × 1019 cm− 3 eV− 1 for no FGA to 3.4 × 1019 cm− 3 eV− 1 for FGA at 450 °C. Furthermore, it is shown that the most pronounced reduction in border trap density estimated from CV hysteresis analysis is observed at the same optimum FGA temperature that reduces the accumulation frequency dispersion, indicating that these two techniques for border trap analysis are correlated. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Elsevier Ltd en
dc.rights © 2017, Elsevier Ltd. All rights reserved. This manuscript version is made available under the CC-BY-NC-ND 4.0 license. en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/4.0/ en
dc.subject Border traps en
dc.subject High-k en
dc.subject InGaAs en
dc.subject CV hysteresis en
dc.subject Accumulation frequency dispersion en
dc.subject Forming gas annealing en
dc.title Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Scott Monaghan, Tyndall Micronano Electronics, University College Cork, Cork, Ireland. +353-21-490-3000 Email: scott.monaghan@tyndall.ie en
dc.internal.availability Full text available en
dc.check.info Access to this article is restricted until 24 months after publication by request of the publisher. en
dc.check.date 2019-05-13
dc.date.updated 2017-09-01T08:56:43Z
dc.description.version Accepted Version en
dc.internal.rssid 409374800
dc.contributor.funder Science Foundation Ireland en
dc.contributor.funder Seventh Framework Programme en
dc.description.status Peer reviewed en
dc.identifier.journaltitle Microelectronic Engineering en
dc.internal.copyrightchecked Yes en
dc.internal.licenseacceptance Yes en
dc.internal.IRISemailaddress scott.monaghan@tyndall.ie en
dc.relation.project info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/619325/EU/Compound Semiconductors for 3D integration/COMPOSE3 en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/688784/EU/Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies/INSIGHT en


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© 2017, Elsevier Ltd. All rights reserved. This manuscript version is made available under the CC-BY-NC-ND 4.0 license. Except where otherwise noted, this item's license is described as © 2017, Elsevier Ltd. All rights reserved. This manuscript version is made available under the CC-BY-NC-ND 4.0 license.
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