Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics

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dc.contributor.author Bolshakov, Pavel
dc.contributor.author Khosravi, Ava
dc.contributor.author Zhao, Peng
dc.contributor.author Hurley, Paul K.
dc.contributor.author Hinkle, Christopher L.
dc.contributor.author Wallace, Robert M.
dc.contributor.author Young, Chadwin D.
dc.date.accessioned 2018-07-03T12:32:44Z
dc.date.available 2018-07-03T12:32:44Z
dc.date.issued 2018-06-19
dc.identifier.citation Bolshakov, P., Khosravi, A., Zhao, P., Hurley, P. K.; Hinkle, C. L., Wallace, R. M. and Young, C. D. (2018) 'Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics', Applied Physics Letters, 112, 253502 (5pp). doi:10.1063/1.5027102 en
dc.identifier.volume 112 en
dc.identifier.issued 25 en
dc.identifier.issn 0003-6951
dc.identifier.issn 1077-3118
dc.identifier.uri http://hdl.handle.net/10468/6407
dc.identifier.doi 10.1063/1.5027102
dc.description.abstract High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s. en
dc.description.sponsorship National Science Foundation (US/Ireland R&D Partnership (UNITE) Award No. ECCS1407765) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher AIP Publishing en
dc.rights © 2018, Article authors. This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Bolshakov, P., Khosravi, A., Zhao, P., Hurley, P. K.; Hinkle, C. L., Wallace, R. M. and Young, C. D. (2018) 'Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics', Applied Physics Letters, 112, 253502 (5pp). doi:10.1063/1.5027102, and may be found at https://doi.org/10.1063/1.5027102 en
dc.subject Dielectric materials en
dc.subject Encapsulation en
dc.subject Field effect transistors en
dc.subject Molybdenum compounds en
dc.title Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Paul Hurley, Tyndall Micronano Electronics, University College Cork, Cork, Ireland. +353-21-490-3000 Email: paul.hurley@tyndall.ie en
dc.internal.availability Full text available en
dc.check.info Access to this article is restricted until 12 months after publication by request of the publisher. en
dc.check.date 2019-06-19
dc.date.updated 2018-07-03T12:20:26Z
dc.description.version Published Version en
dc.internal.rssid 443941714
dc.contributor.funder National Science Foundation en
dc.contributor.funder Science Foundation Ireland en
dc.description.status Peer reviewed en
dc.identifier.journaltitle Applied Physics Letters en
dc.internal.copyrightchecked Yes en
dc.internal.licenseacceptance Yes en
dc.internal.IRISemailaddress paul.hurley@tyndall.ie en
dc.identifier.articleid 253502
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI US Ireland R&D Partnership/13/US/I2862/IE/Understanding the Nature of Interfaces in Two Dimensional Electronic Devises (UNITE)/ en


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