The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices

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dc.contributor.author Gammon, P. M.
dc.contributor.author Li, F.
dc.contributor.author Chan, C. W.
dc.contributor.author Sanchez, A.
dc.contributor.author Hindmarsh, S.
dc.contributor.author Gity, Farzan
dc.contributor.author Trajkovic, T.
dc.contributor.author Kilchytska, V.
dc.contributor.author Pathirana, V.
dc.contributor.author Camuso, G.
dc.contributor.author Ben Ali, K.
dc.contributor.author Flandre, Denis
dc.contributor.author Mawby, P. A.
dc.contributor.author Gardner, J. W.
dc.date.accessioned 2018-07-30T12:30:36Z
dc.date.available 2018-07-30T12:30:36Z
dc.date.issued 2017
dc.identifier.citation P. M. Gammon et al. (2017) ‘The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices’, Materials Science Forum, 897, pp. 747-750. doi: 10.4028/www.scientific.net/MSF.897.747 en
dc.identifier.volume 897
dc.identifier.startpage 747
dc.identifier.endpage 750
dc.identifier.issn 0255-5476
dc.identifier.issn 1662-9752
dc.identifier.uri http://hdl.handle.net/10468/6548
dc.identifier.doi 10.4028/www.scientific.net/MSF.897.747
dc.description.abstract A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Trans Tech Publications Ltd en
dc.rights © 2017, Trans Tech Publications Inc. All rights reserved. en
dc.subject Harsh environment en
dc.subject Lateral MOSFET en
dc.subject Silicon en
dc.subject Silicon carbide en
dc.subject SiC en
dc.subject Wafer bonding en
dc.title The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Farzan Gity, Tyndall National Institute, University College Cork, Cork, Ireland +353-21-490-3000 Email: farzan.gity@tyndall.ie en
dc.internal.availability Full text available en
dc.description.version Accepted Version en
dc.contributor.funder Horizon 2020
dc.contributor.funder Royal Academy of Engineering
dc.contributor.funder Engineering and Physical Sciences Research Council
dc.description.status Peer reviewed en
dc.identifier.journaltitle Materials Science Forum en
dc.internal.IRISemailaddress farzan.gity@tyndall.ie en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/687361/EU/Si on SiC for the Harsh Environment of Space/SaSHa
dc.relation.project info:eu-repo/grantAgreement/RCUK/EPSRC/EP/N00647X/1/GB/Silicon-Silicon Carbide (Si/SiC) Power Devices for high temperature, hostile environment applications/


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