Technology platform for the fabrication of micro-inductors on silicon for dc-dc conversion

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dc.contributor.advisor O Mathuna, Cian en
dc.contributor.advisor Rohan, James en
dc.contributor.author Anthony, Ricky
dc.date.accessioned 2018-09-12T10:47:16Z
dc.date.issued 2018
dc.date.submitted 2018
dc.identifier.citation Anthony, R. 2018. Technology platform for the fabrication of micro-inductors on silicon for dc-dc conversion. PhD Thesis, University College Cork. en
dc.identifier.endpage 258 en
dc.identifier.uri http://hdl.handle.net/10468/6756
dc.description.abstract Power conversion circuitry is an integral part of electronic devices such as in handheld mobile devices and laptops. With the on-going trend towards miniaturization of electronic components, a significant challenge will be to deliver high efficiency power management solutions. Switch mode DC-DC power supplies (SMPS) in particular are highly efficient and have high power density. The power passive components in SMPS such as inductors which take up almost 30% of the designed power conversion circuitry are usually bulky, discrete and off the shelf components which have to be miniaturized further for possible integration with power management ICs for high-frequency applications without compromising on its efficiency. In recent years, an increase in switching frequencies (> 10 MHz) and with soft magnetic core technology, these magnetic components have been miniaturized below 2 mm2 . These inductors can now be integrated in-package (PwrSiP) with power ICs with the ultimate aim to increase integration and reliability by realizing a monolithically integrated power supply on chip (PwrSoC). This has led to substantial interest in the area, from both industry and academia. Although there have been significant developments in component design to achieve efficient and miniaturized micro-inductors, on-silicon CMOS compatible process technology requires further development for miniaturization and losses remain a significant roadblock. This dissertation focusses on process solutions to the challenges by providing new fabrication routes that reduce the inductor losses, increase batch yield, integration and reliability. The processes developed are integrated to realize the first closed core solenoid micro-inductor. Firstly, to reduce DC winding losses, a high resolution (~ 5 µm) and high aspect ratio (17:1) single-spin metal moulding technology has been developed. Thick copper air-core inductor micro-windings (~80 µm) with varying winding width (5 µm to 25 µm) and footprint (0.36 mm2 -1.9 mm2 ) were fabricated. The 80 µm thick windings and 5 µm spacing (0.39 mm2 ) suggested ~ 42 % reduction in resistance (from 273 mΩ to 159 mΩ ) compared to 50 µm thick windings and 10 µm spacing (0.45 mm2 ).This is a cost-effective process for miniaturization and reducing DC winding losses by comparison with multi-spin, low resolution and low aspect ratio processes. Secondly, to reduce magnetic core loss, a borane based variable composition (Permalloy Ni80Fe20 to Invar Ni37Fe63) electroless bath has been developed. This has been shown to give greater selection of the core in terms of magnetic (96 A/m for Ni37Fe63- 26.6 A/m for Ni81Fe19) and electrical resistivity (26 µOhm-cm for Ni81Fe19 - 62 µOhm-cm for Ni37Fe63). In-parallel, an electrochemical post-processed ultra-soft magnetic film material has been developed with coercivity < 5 A/m, anisotropy field > 900 A/m, saturation flux density ~ 1.4 T and resistivity > 65 µOhm-cm. The post-processed film showed a reduction of the as-deposited coercivity from 30 A/m to 1.5 A/m whereas the anisotropy field improved from 735 A/m to 954 A/m along the hard-axis. The high frequency real permeability response of 1.65 µm thick film at zero bias suggested an initial permeability > 550 with a cut-off frequency ~ 120 MHz. Both sputter and electrochemical deposition routes have been explored to laminate the magnetic films which could restrict the eddy current losses at high frequencies. A site-selective metallization process on dielectrics (such as SU-8, BCB and parylene-C) without sputtered blanket seed layers through cost-effective electrochemical route has been developed as a route to core-laminations. Sputtered spacer films (Ta(N)) with Permalloy have been shown to improve anisotropy and high-frequency properties. Finally a first closed core solenoid micro-inductor prototype has been fabricated. The device was FEM simulated, analytically designed and micro-fabricated in a 3-D closed-core solenoid inductor. The top windings of the device were realized by integrating the HAR photoresist process developed. The Ni-Fe (45/55) core was realized using an in-house developed electroplating process. The closed core design suggested a two-fold increase in inductance compared to an open core design. The fabricated 3-D closed core micro-inductor has an inductance of ~ 54 nH with winding DC resistance of ~ 220 mΩ and saturation current of ~ 500 mA. The device has a footprint area of ~ 0.75 mm2 and an inductance density of 72 nH/mm2 . This miniaturized and high inductance device would be ideal for integration with power management ICs for high-frequency power conversion applications. Compared to FEN simulated air-core and open core designs, inductance can be further increased by a factor of 12.4 and 1.95 respectively, with the closed core design. The inductance densities for the air-core, open-core and closed core designs are 5.6 nH/mm2 , 36 nH/mm2 and 68 nH/mm2 respectively. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2018, Ricky Anthony. en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject Magnetics en
dc.subject MEMS en
dc.subject Inductors en
dc.subject Transformers en
dc.subject Magnetic materials en
dc.subject Power magnetics en
dc.title Technology platform for the fabrication of micro-inductors on silicon for dc-dc conversion en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PhD en
dc.internal.availability Full text not available en
dc.check.info Restricted to everyone for five years en
dc.check.date 2023-09-11T10:47:16Z
dc.description.version Accepted Version
dc.contributor.funder Seventh Framework Programme en
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.check.reason This thesis contains data which has not yet been published en
dc.check.opt-out Yes en
dc.thesis.opt-out true
dc.check.entireThesis Entire Thesis Restricted
dc.check.embargoformat Apply the embargo to both hard bound copy and e-thesis (If you have submitted an e-thesis and a hard bound thesis and want to embargo both) en
dc.internal.conferring Autumn 2018 en
dc.internal.ricu Tyndall National Institute en
dc.relation.project info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/318529/EU/POWER SoC With Integrated PassivEs/POWERSWIPE en


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