Investigating electrically active defect distributions in MOS structures based on inelastic tunneling interaction with border traps and a nonlocal model for interface traps

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dc.contributor.author Caruso, Enrico
dc.contributor.author Lin, Jun
dc.contributor.author Monaghan, Scott
dc.contributor.author Cherkaoui, Karim
dc.contributor.author Gity, Farzan
dc.contributor.author Palestri, Pierpaolo
dc.contributor.author Esseni, David
dc.contributor.author Selmi, Luca
dc.contributor.author Hurley, Paul K.
dc.date.accessioned 2019-05-03T13:46:02Z
dc.date.available 2019-05-03T13:46:02Z
dc.date.issued 2019-07-03
dc.identifier.citation Caruso, E.; Lin, J.; Monaghan, S.; Cherkaoui, K.; Gity, F.; Palestri, P.; Esseni, D.; Selmi, L.; Hurley, Paul K. (2019) ‘Investigating electrically active defect distributions in MOS structures based on inelastic tunneling interaction with border traps and a nonlocal model for interface traps’, INFOS 2019, Cambridge University, UK. 31 June-3 July, Forthcoming. en
dc.identifier.startpage 1 en
dc.identifier.endpage 2 en
dc.identifier.uri http://hdl.handle.net/10468/7854
dc.description.abstract This work demonstrates that when inelastic band-to-trap tunneling is considered, border traps aligned with the semiconductor bandgap play a significant role in the C-V/G-V dispersion of a MOS structure. In addition, for the case of quantization, a non-local model for interface states is required. The model is used to evaluate the energy/depth distribution of border traps in a n-In0.53Ga0.47As /Al2O3 MOS system. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.relation.uri https://infos2019-conf.org/
dc.rights © 2019 The Authors. en
dc.subject MOS structures en
dc.subject Border traps en
dc.subject Interface traps en
dc.subject Capacitance - voltage en
dc.subject MOS systems en
dc.subject Quantization model en
dc.title Investigating electrically active defect distributions in MOS structures based on inelastic tunneling interaction with border traps and a nonlocal model for interface traps en
dc.type Conference item en
dc.internal.authorcontactother Enrico Caruso, Tyndall National Institute, University College Cork, Cork, Ireland. T: +353-21-490-3000 E: enrico.caruso@tyndall.ie en
dc.internal.availability Full text available en
dc.description.version Accepted Version en
dc.contributor.funder Horizon 2020 en
dc.description.status Peer reviewed en
dc.internal.IRISemailaddress enrico.caruso@tyndall.ie en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/688784/EU/Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies/INSIGHT en


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