A systematic review of blockchain hardware acceleration architectures

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dc.contributor.author O'Mahony, Aidan T.
dc.contributor.author Popovici, Emanuel M.
dc.date.accessioned 2019-10-01T11:17:32Z
dc.date.available 2019-10-01T11:17:32Z
dc.date.issued 2019-06
dc.identifier.citation O'Mahony, A. and Popovici, E. (2019) 'A Systematic Review of Blockchain Hardware Acceleration Architectures', 30th Irish Signals and Systems Conference (ISSC 2019) Maynooth, Ireland, 17-18 June. doi: 10.1109/ISSC.2019.8904936 en
dc.identifier.startpage 1 en
dc.identifier.endpage 6 en
dc.identifier.isbn 978-1-7281-2800-9
dc.identifier.uri http://hdl.handle.net/10468/8655
dc.identifier.doi 10.1109/ISSC.2019.8904936
dc.description.abstract The aim of this paper is to provide a systematic literature review of blockchain hardware acceleration. Blockchain technology has achieved significant attention in recent years particularly in the area of cryptocurrency however it is gaining popularity in other applications such as supply chain management and e-government. Based on a structured, systematic review of the relevant literature, we present a classification of the primary areas in blockchain technology that make use of heterogeneous hardware for accelerating certain blockchain functions. Based on these findings, we identify various research gaps and future exploratory directions that are anticipated to be of significant value both for academics and industry practitioners. en
dc.description.sponsorship Intel Corporation (Intel Programmable Solutions Group); en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.uri https://ieeexplore.ieee.org/document/8904936
dc.rights © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject Blockchain en
dc.subject Distributed ledger technology en
dc.subject Hardware architecture en
dc.subject Systematic literature review en
dc.subject Consensus algorithms en
dc.subject Heterogeneous hardware en
dc.subject FPGA en
dc.subject GPU en
dc.subject ASIC en
dc.subject CPU en
dc.title A systematic review of blockchain hardware acceleration architectures en
dc.type Conference item en
dc.internal.authorcontactother Aidan O'Mahony, Electrical & Electronic Engineering, University College Cork, Cork, Ireland. +353-21-490-3000 en
dc.internal.availability Full text available en
dc.date.updated 2019-10-01T11:04:42Z
dc.description.version Accepted Version en
dc.internal.rssid 499777242
dc.contributor.funder Intel Corporation en
dc.contributor.funder Science Foundation Ireland en
dc.description.status Peer reviewed en
dc.internal.copyrightchecked Yes
dc.internal.licenseacceptance Yes en
dc.internal.conferencelocation Maynooth, Ireland en
dc.internal.IRISemailaddress e.popovici@ucc.ie en
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI Research Centres/12/RC/2289/IE/INSIGHT - Irelands Big Data and Analytics Research Centre/ en

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