Relationship between capacitance and conductance in MOS capacitors

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dc.contributor.author Caruso, Enrico
dc.contributor.author Lin, Jun
dc.contributor.author Monaghan, Scott
dc.contributor.author Cherkaoui, Karim
dc.contributor.author Floyd, Liam
dc.contributor.author Gity, Farzan
dc.contributor.author Palestri, Pierpaolo
dc.contributor.author Esseni, David
dc.contributor.author Selmi, Luca
dc.contributor.author Hurley, Paul K.
dc.date.accessioned 2019-10-29T09:56:45Z
dc.date.available 2019-10-29T09:56:45Z
dc.date.issued 2019-09
dc.identifier.citation Caruso, E., Lin, J., Monaghan, S., Cherkaoui, K., Floyd, L., Gity, F., Palestri, P., Esseni, D., Selmi, L. and Hurley, P. K. (2019) 'Relationship between capacitance and conductance in MOS capacitors', 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, 4-6 Sept. 2019, (4 pp). doi: 10.1109/SISPAD.2019.8870553 en
dc.identifier.startpage 1 en
dc.identifier.endpage 4 en
dc.identifier.isbn 978-1-7281-0940-4
dc.identifier.isbn 978-1-7281-0939-8
dc.identifier.isbn 978-1-7281-0941-1
dc.identifier.issn 1946-1577
dc.identifier.issn 1946-1569
dc.identifier.uri http://hdl.handle.net/10468/8908
dc.identifier.doi 10.1109/SISPAD.2019.8870553 en
dc.description.abstract In this work, we describe how the frequency dependence of conductance (G) and capacitance (C) of a generic MOS capacitor results in peaks of the functions G/ω and -ωdC/dω. By means of TCAD simulations, we show that G/ω and -ωdC/dω peak at the same value and at the same frequency for every bias point from accumulation to inversion. We illustrate how the properties of the peaks change with the semiconductor doping (ND), oxide capacitance (COX), minority carrier lifetime (τg), interface defect parameters (NIT, σ) and majority carrier dielectric relaxation time (τr). Finally, we demonstrate how these insights on G/ω and -ωdC/dω can be used to extract COX, ND and τg from InGaAs MOSCAP measurements. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.uri https://ieeexplore.ieee.org/document/8870553
dc.rights © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject Capacitance en
dc.subject MOS capacitors en
dc.subject Indium gallium arsenide en
dc.subject Semiconductor device measurement en
dc.subject Frequency modulation en
dc.subject Capacitance-voltage characteristics en
dc.subject Frequency measurement en
dc.subject Characterization en
dc.subject extraction technique en
dc.subject MOS en
dc.subject multi-frequency en
dc.subject C-V en
dc.subject G-V en
dc.subject Minority carrier lifetime en
dc.subject Oxide capacitance en
dc.subject Doping en
dc.title Relationship between capacitance and conductance in MOS capacitors en
dc.type Conference item en
dc.internal.authorcontactother Enrico Caruso, Tyndall Micronano Electronics, University College Cork, Cork, Ireland. +353-21-490-3000 Email: enrico.caruso@tyndall.ie en
dc.internal.availability Full text available en
dc.date.updated 2019-10-29T09:45:59Z
dc.description.version Accepted Version en
dc.internal.rssid 499909585
dc.contributor.funder Science Foundation Ireland en
dc.contributor.funder Horizon 2020 en
dc.description.status Peer reviewed en
dc.internal.copyrightchecked No
dc.internal.licenseacceptance Yes en
dc.internal.conferencelocation Udine, Italy en
dc.internal.IRISemailaddress enrico.caruso@tyndall.ie en
dc.internal.IRISemailaddress paul.hurley@tyndall.ie en
dc.internal.IRISemailaddress jun.lin@tyndall.ie en
dc.internal.IRISemailaddress scott.monaghan@tyndall.ie en
dc.internal.IRISemailaddress karim.cherkaoui@tyndall.ie en
dc.internal.IRISemailaddress liam.floyd@tyndall.ie
dc.internal.IRISemailaddress farzan.gity@tyndall.ie en
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI Investigator Programme/15/IA/3131/IE/Investigating Emerging 2D Semiconductor Technology/ en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/688784/EU/Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies/INSIGHT en


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