Demonstration of genuine surface inversion for the p/n-In0.3Ga0.7Sb-Al2O3 MOS system with in situ H2 plasma cleaning

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dc.contributor.author Millar, David A. J.
dc.contributor.author Peralagu, Uthayasankaran
dc.contributor.author Li, Xu
dc.contributor.author Steer, Matthew J.
dc.contributor.author Fu, Yen-Chun
dc.contributor.author Hurley, Paul K.
dc.contributor.author Thayne, Iain G.
dc.date.accessioned 2019-12-20T11:48:20Z
dc.date.available 2019-12-20T11:48:20Z
dc.date.issued 2019-12-02
dc.identifier.citation Millar, D. A. J., Peralagu, U., Li, X., Steer, M. J., Fu, Y.-C., Hurley, P. K. and Thayne, I. G. (2019) 'Demonstration of genuine surface inversion for the p/n-In0.3Ga0.7Sb-Al2O3 MOS system with in situ H2 plasma cleaning', Applied Physics Letters, 115(23), 231602 (5pp). doi: 10.1063/1.5122731 en
dc.identifier.volume 115 en
dc.identifier.issued 23 en
dc.identifier.startpage 1 en
dc.identifier.endpage 5 en
dc.identifier.issn 0003-6951
dc.identifier.uri http://hdl.handle.net/10468/9443
dc.identifier.doi 10.1063/1.5122731 en
dc.description.abstract The results of an investigation into the impact of in situ H2 plasma exposure on the electrical properties of the p/n-In0.3 Ga0.7 Sb-Al2O3 interface are presented. Samples were processed using a clustered inductively coupled plasma reactive ion etching and atomic layer deposition tool. Metal oxide semiconductor capacitors were fabricated subsequent to H2 plasma processing and Al2O3 deposition, and the corresponding capacitance-voltage and conductance-voltage measurements were analyzed quantitatively via the simulation of an equivalent circuit model. Interface state (Dit) and border trap (Nbt) densities were extracted for samples subjected to the optimal process, with a minimum Dit of 1.73×1012 eV−1 cm−2 located at ∼110 meV below the conduction band edge and peak Nbt approximately aligned with the valence and conduction band edges of 3×1019 cm−3 and 6.5×1019 cm−3, respectively. Analysis of the inversion response in terms of the extraction of the activation energy of minority carriers in inversion (p-type) and the observation of characteristics that pertain to minority carriers being supplied from an external inversion region (n-type) unequivocally demonstrate that the Fermi level is unpinned and that genuine surface inversion is observed for both doping polarities. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher AIP Publishing en
dc.relation.uri https://aip.scitation.org/doi/abs/10.1063/1.5122731
dc.rights © 2019, the Authors. Published under license by AIP Publishing. This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared as: Millar, D. A. J., Peralagu, U., Li, X., Steer, M. J., Fu, Y.-C., Hurley, P. K. and Thayne, I. G. (2019) 'Demonstration of genuine surface inversion for the p/n-In0.3Ga0.7Sb-Al2O3 MOS system with in situ H2 plasma cleaning', Applied Physics Letters, 115(23), 231602 (5pp), doi: 10.1063/1.5122731, and may be found at https://doi.org/10.1063/1.5122731 en
dc.subject H2 plasma exposure en
dc.subject Fermi level en
dc.subject Surface inversion en
dc.subject p/n-In0.3 Ga0.7 Sb-Al2O3 en
dc.title Demonstration of genuine surface inversion for the p/n-In0.3Ga0.7Sb-Al2O3 MOS system with in situ H2 plasma cleaning en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Paul Hurley, Tyndall Micronano Electronics, University College Cork, Cork, Ireland. +353-21-490-3000 Email: paul.hurley@tyndall.ie en
dc.internal.availability Full text available en
dc.check.info Access to this article is restricted until 12 months after publication by request of the publisher. en
dc.check.date 2020-12-02
dc.date.updated 2019-12-20T11:41:20Z
dc.description.version Published Version en
dc.internal.rssid 500171256
dc.contributor.funder Horizon 2020 en
dc.description.status Peer reviewed en
dc.identifier.journaltitle Applied Physics Letters en
dc.internal.copyrightchecked Yes
dc.internal.licenseacceptance Yes en
dc.internal.IRISemailaddress paul.hurley@tyndall.ie en
dc.identifier.articleid 231602 en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/688784/EU/Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies/INSIGHT en
dc.identifier.eissn 1077-3118


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