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oai:cora.ucc.ie:10468/124832023-04-04T10:49:48Zcom_10468_388com_10468_5com_10468_347com_10468_1com_10468_41com_10468_6col_10468_9859col_10468_10013col_10468_8983col_10468_10638

embargoed 2025-05-30 O'Hare, Daniel O'Connell, Ivan Zheng, Hao 2022-01-26T15:35:50Z 2022-01-26T15:35:50Z 2021-06 2021-06 This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW. Not peer reviewed Accepted Version application/pdf Zheng, H. 2021. Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources. MRes Thesis, University College Cork. 144 https://hdl.handle.net/10468/12483 en University College Cork © 2021, Hao Zheng. https://creativecommons.org/licenses/by-sa/4.0/ Mixed signal compensation DPLL clock sources Sampling errors in ADCs Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources Masters thesis (Research) Masters MRes - Master of Researchinfo:eu-repo/semantics/openAccess