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McCarthy, Kevin G. O'Connell, Ivan Molina Salgado, Gerardo Kalogiros, Spyridon Science Foundation Ireland Analog Devices Incorporation (ADI) 2025-05-12T13:27:52Z 2025-05-12T13:27:52Z 2025 2025 Since analogue information in our world is abundant, such as light, temperature, sound, voltage, current, and others, Analogue-to-Digital Converters (ADCs) are the key electronic components for the communication with the digital world, where all the signal processing in modern electronic systems takes place. The ongoing demand for power-efficient ADCs is ever more present, driven by rapidly increasing energy costs and the need to minimize self-heating in deep sub-micron nodes. As the ADCs are typically categorised into technology-limited and noise-limited, the power efficiency of the former is benchmarked by the Walden Figure-of-Merit (FoMW), and the latter, by the Schreier Figure-of-Merit (FoMS). Technology scaling over the past decades has indicated that FoMS, in noise-limited ADCs, captures more precisely the power efficiency than its counterpart. While the performance of noise-limited ADCs has advanced significantly over the last 20 years, as quantified by FoMS, the theoretical FoMS boundary of 192 dB remains unchallenged. Over that period, the envelope of ADC performance has advanced from a FoMS of 163 dB 20 years ago, to 186 dB today, with a rate of advancement, corresponding to ADC performance, which is doubling every 1.6 years. However, this rate of advancement has started to slow in recent years. The present thesis firstly reviews the fundamentals of the Analogue-to-Digital conversion process, and outlines the most important ADC structures of the current state-of-the-art. It presents the theory behind thermal noise components in noise-limited ADCs which play a crucial role in the Figure-of-Merit performance. Additionally, it studies the 192 dB fundamental limitation of FoMS, imposed by the laws of physics in analogue circuits, and compares the current state-of-the-art with these limits. Techniques of cancelling thermal noise in ADCs from the current state-of-the-art are also discussed. A new design is proposed towards the approach of the 192 dB FoMS barrier, mainly breaking the practical limit of 186-188 dB, which has been approached from recent publications. This is a feed-forward Delta-Sigma Modulator (DSM), hybridised with a Successive Approximation Register (SAR) ADC as a quantiser, which also takes the role of a summing node, to further reduce the power consumption. A continuous-time amplification front-end is added before the loop-filter, significantly reducing the input-referred thermal noise density, which is a key factor for the FoMS advancement. Simulations are provided both in the system-level domain, using the Python language, and at the transistor-level design, using the circuit simulator “Spectre”. Finally, the conclusions and the research publications of this work are presented, paving the way for more power-efficient ADC circuit designs in the future, and thus, enabling the electronic devices to operate in a more environmental-friendly manner. Not peer reviewed Accepted Version application/pdf Kalogiros, S. 2025. Design techniques for Power-Efficient Delta-Sigma Analogue-to-Digital Converters. PhD Thesis, University College Cork. 199 https://hdl.handle.net/10468/17420 en University College Cork info:eu-repo/grantAgreement/SFI/SFI Research Centres/13/RC/2077/IE/CONNECT: The Centre for Future Networks & Communications/ © 2025, Spyridon Kalogiros. https://creativecommons.org/licenses/by-nc-nd/4.0/ Delta-Sigma Modulators ADCs Power efficiency Analogue-to-Digital Converters Design techniques for Power-Efficient Delta-Sigma Analogue-to-Digital Converters Doctoral thesis Doctoral PhD - Doctor of Philosophyinfo:eu-repo/semantics/openAccess