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oai:cora.ucc.ie:10468/53492023-04-04T07:03:41Zcom_10468_1com_10468_41com_10468_6col_10468_140col_10468_3619

Not applicable No embargo required Not applicable No embargo required No Embargo Required Hurley, Paul K. Monaghan, Scott Lin, Jun Science Foundation Ireland Seventh Framework Programme 2018-01-30T12:47:49Z 2018-01-30T12:47:49Z 2017 2017 One approach to saving energy in metal-oxide-semiconductor field effect transistors (MOSFETs) is to replace SiO2/Si structure with high dielectric constant (high-k) oxides on high mobility channel materials (e.g. InGaAs), which have the potential to achieve a comparable on current and operating frequency to silicon, but at a reduced supply voltage. In this thesis, investigation into border traps (or charge trapping) and interface states, both of which can induce device instability, in HfO2/InGaAs and Al2O3/InGaAs metal-oxidesemiconductor (MOS) structures was carried out with an emphasis on the characterization of border traps using capacitance-voltage (C-V) hysteresis measurement. The charge trapping is observed to be mainly a reversible process. The trapped charge is predominantly localized as a sheet charge near/at the high-k/InGaAs interfacial layer (~1nm), which can contain native oxides of InGaAs. The engineering of the high-k/InGaAs interface is therefore the key to reducing C-V hysteresis and improving device reliability. This work demonstrates the ability to reduce border trap density with forming gas annealing (5% H2 / 95% N2) in the range 3500C~4500C for Al2O3/InGaAs and HfO2/InGaAs MOS structures. Moreover, it is observed that C-V hysteresis increases with a power law dependence with the increasing stress time (in accumulation) at the initial stage of stressing and tends to reach a plateau at sufficiently long stress times due to the filling of almost all the pre-existing border traps. This therefore provides a method to estimate the total trap density under certain oxide field. Furthermore, a combined C-V and hard x-ray photoelectron spectroscopy (HAXPES) study was performed on Al2O3/InGaAs MOS structure, revealing a partially pinned Al2O3/InGaAs interface. The Fermi level position at zero gate bias was calculated using both techniques, and a reasonable agreement was achieved. This combined study thus provides more certainty on the interface state profile extractions. Not peer reviewed Accepted Version application/pdf Lin, J. 2017. An investigation of border traps and interface states in high-k/InGaAs metal-oxide-semiconductor systems. PhD Thesis, University College Cork. 164 https://hdl.handle.net/10468/5349 en University College Cork info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/619325/EU/Compound Semiconductors for 3D integration/COMPOSE3 info:eu-repo/grantAgreement/SFI/SFI Principal Investigator Programme (PI)/09/IN.1/I2633/IE/Investigating Emerging Non-Silicon Transistors (INVENT)/ © 2017, Jun Lin. http://creativecommons.org/licenses/by-nc-nd/3.0/ InGaAs MOS Border traps Interface states false An investigation of border traps and interface states in high-k/InGaAs metal-oxide-semiconductor systems Doctoral thesis Doctoral PhD (Science) paul.hurley@tyndall.ieinfo:eu-repo/semantics/openAccess