Hardware reduction in digital delta-sigma modulators via error masking - part I: MASH DDSM

Files in this item

Icon
Name: ZY_HardwarePV2009.pdf
Size: 3.857Mb
Format: PDF
Description: Published Version
View/Open

Hardware reduction in digital delta-sigma modulators via error masking - part I: MASH DDSM

Ye, Zhipeng; Kennedy, Michael Peter
Date: 2009-04
Copyright: ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Citation: Ye, ZP, Kennedy, MP (2009) 'Hardware Reduction In Digital Delta-Sigma Modulators Via Error Masking-Part I: Mash Ddsm'. Ieee Transactions On Circuits and Systems I-Regular Papers, 56 (4):714-726.
Published Version: 10.1109/TCSI.2008.2003383

Abstract:

Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs..

Show full item record

This item appears in the following Collection(s)

This website uses cookies. By using this website, you consent to the use of cookies in accordance with the UCC Privacy and Cookies Statement. For more information about cookies and how you can disable them, visit our Privacy and Cookies statement