Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources

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dc.availability.bitstreamembargoed
dc.check.date2025-05-30
dc.contributor.advisorO'Hare, Danielen
dc.contributor.advisorO'Connell, Ivanen
dc.contributor.authorZheng, Hao
dc.date.accessioned2022-01-26T15:35:50Z
dc.date.available2022-01-26T15:35:50Z
dc.date.issued2021-06
dc.date.submitted2021-06
dc.description.abstractThis thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW.en
dc.description.statusNot peer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationZheng, H. 2021. Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources. MRes Thesis, University College Cork.en
dc.identifier.endpage144en
dc.identifier.urihttps://hdl.handle.net/10468/12483
dc.language.isoenen
dc.publisherUniversity College Corken
dc.rights© 2021, Hao Zheng.en
dc.rights.urihttps://creativecommons.org/licenses/by-sa/4.0/en
dc.subjectMixed signal compensationen
dc.subjectDPLL clock sourcesen
dc.subjectSampling errors in ADCsen
dc.titleMixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sourcesen
dc.typeMasters thesis (Research)en
dc.type.qualificationlevelMastersen
dc.type.qualificationnameMRes - Master of Researchen
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