Low subthreshold slope in junctionless multigate transistors

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dc.contributor.authorLee, Chi-Woo
dc.contributor.authorNazarov, Alexei N.
dc.contributor.authorFerain, Isabelle
dc.contributor.authorAkhavan, Nima Dehdashti
dc.contributor.authorYan, Ran
dc.contributor.authorRazavi, Pedram
dc.contributor.authorYu, Ran
dc.contributor.authorDoria, Rodrigo T.
dc.contributor.authorColinge, Jean-Pierre
dc.contributor.funderScience Foundation Ireland
dc.contributor.funderSeventh Framework Programme
dc.date.accessioned2017-07-28T11:22:09Z
dc.date.available2017-07-28T11:22:09Z
dc.date.issued2010
dc.description.abstractThe improvement of subthreshold slope due to impact ionization is compared between "standard" inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope. (C) 2010 American Institute of Physics. (doi: 10.1063/1.3358131)en
dc.description.sponsorshipScience Foundation Ireland (Grant No. 05/IN/I888)en
dc.description.statusPeer revieweden
dc.description.versionPublished Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.articleid102106
dc.identifier.citationLee, C.-W., Nazarov, A. N., Ferain, I., Akhavan, N. D., Yan, R., Razavi, P., Yu, R., Doria, R. T. and Colinge, J.-P. (2010) 'Low subthreshold slope in junctionless multigate transistors', Applied Physics Letters, 96(10), pp. 102106. doi: 10.1063/1.3358131en
dc.identifier.doi10.1063/1.3358131
dc.identifier.endpage3
dc.identifier.issn0003-6951
dc.identifier.issn1077-3118
dc.identifier.issued10
dc.identifier.journaltitleApplied Physics Lettersen
dc.identifier.startpage1
dc.identifier.urihttps://hdl.handle.net/10468/4345
dc.identifier.volume96
dc.language.isoenen
dc.publisherAIP Publishingen
dc.relation.projectinfo:eu-repo/grantAgreement/EC/FP7::SP1::ICT/216171/EU/Silicon-based nanostructures and nanodevices for long term nanoelectronics applications/NANOSIL
dc.relation.projectinfo:eu-repo/grantAgreement/EC/FP7::SP1::ICT/216373/EU/European platform for low-power applications on Silicon-on-Insulator Technology/EUROSOI+
dc.relation.urihttp://aip.scitation.org/doi/abs/10.1063/1.3358131
dc.rights© 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Lee, C.-W., Nazarov, A. N., Ferain, I., Akhavan, N. D., Yan, R., Razavi, P., Yu, R., Doria, R. T. and Colinge, J.-P. (2010) 'Low subthreshold slope in junctionless multigate transistors', Applied Physics Letters, 96(10), pp. 102106 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3358131en
dc.subjectImpact ionizationen
dc.subjectSiliconen
dc.subjectIonizationen
dc.subjectMOSFETsen
dc.subjectDopingen
dc.subjectSiliconen
dc.subjectBand gapen
dc.titleLow subthreshold slope in junctionless multigate transistorsen
dc.typeArticle (peer-reviewed)en
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