Development, characterisation and simulation of wafer bonded Si-on-SiC substrates

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dc.contributor.authorGammon, P. M.
dc.contributor.authorChan, C. W.
dc.contributor.authorLi, F.
dc.contributor.authorGity, Farzan
dc.contributor.authorTrajkovic, T.
dc.contributor.authorPathirana, V.
dc.contributor.authorFlandre, Denis
dc.contributor.authorKilchytska, V.
dc.contributor.funderHorizon 2020 Framework Programme
dc.contributor.funderEuropean Commission
dc.contributor.funderRoyal Academy of Engineering
dc.contributor.funderEngineering and Physical Sciences Research Council
dc.date.accessioned2018-06-15T11:47:11Z
dc.date.available2018-06-15T11:47:11Z
dc.date.issued2018
dc.description.abstractNovel silicon-on-silicon carbide (Si/SiC) substrates are being developed in order to produce lateral power devices for harsh environment applications. Two methods of producing 100 mm Si/SiC substrates are detailed by wafer bonding silicon-on-insulator (SOI) wafers to semi-insulating 4H-SiC, then removing the SOI handle wafer and buried oxide. The final process includes a radical activation bonding process with low temperature processing , resulting in 97% yield. A uniform oxide layer at the Si/SiC interface of 1.4-1.8 nm is revealed, without voids, which minimises charge density at this interface. Capacitance-voltage (C-V) measurements of lateral metal-oxide-semiconductor capacitors (LMOS-Cs) are carried out on both processes revealing what appears to be an inversion from an n-type to a p-type like response in the 2 mu m layers. Thinning the Si layers to 1 mu m and making new LMOS-Cs, C-V responses show an improved n-type-like response, though frequency dispersion and incomplete accumulation remain. Finite element simulations showed that this effect could be reproduced by the introduction of interfacial charge at the two interfaces. Finally, while one possible explanation for fully inverting the C-V response of an n-type 2 mu m Si layer on SiC was shown, the full understanding for this remains to be further studied.en
dc.description.sponsorshipEngineering and Physical Sciences Research Council (EP/N00647X/1)en
dc.description.statusPeer reviewed
dc.description.versionPublished Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationGammon, P. M., Chan, C. W., Li, F., Gity, F., Trajkovic, T., Pathirana, V., Flandre, D. and Kilchytska, V. (2018) 'Development, characterisation and simulation of wafer bonded Si-on-SiC substrates', Materials Science in Semiconductor Processing, 78, pp. 69-74. doi: 10.1016/j.mssp.2017.10.020en
dc.identifier.doi10.1016/j.mssp.2017.10.020
dc.identifier.endpage74
dc.identifier.issn1369-8001
dc.identifier.journaltitleMaterials Science in Semiconductor Processingen
dc.identifier.startpage69
dc.identifier.urihttps://hdl.handle.net/10468/6328
dc.identifier.volume78
dc.language.isoenen
dc.publisherElsevier Ltden
dc.relation.projectinfo:eu-repo/grantAgreement/EC/H2020::RIA/687361/EU/Si on SiC for the Harsh Environment of Space/SaSHa
dc.relation.urihttps://www.sciencedirect.com/science/article/pii/S136980011731805X
dc.rights© 2017, the Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/BY-NC-ND/4.0/).en
dc.rights.urihttp://creativecommons.org/licenses/BY-NC-ND/4.0/
dc.subjectSilicon carbideen
dc.subjectWafer bondingen
dc.subjectSi/SiCen
dc.subjectPower electronic devicesen
dc.subjectInterfacial chargeen
dc.subjectMos capacitorsen
dc.titleDevelopment, characterisation and simulation of wafer bonded Si-on-SiC substratesen
dc.typeArticle (peer-reviewed)en
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