ELEVATE: Optimal scheduling of time-sensitive tasks on the heterogeneous reconfigurable edge
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Date
2025-02-04
Authors
Hoyer, Ingo
Zaarour, Tarek
Khalid, Ahmed
Utz, Alexander
Seidl, Karsten
Brown, Ken
Zahran, Ahmed H.
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Institute of Electrical and Electronics Engineers (IEEE)
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Abstract
Edge computing is evolving to include heterogeneous compute nodes with distinct characteristics. Graphic processing units (GPU) and field-programmable gate arrays (FPGA) can execute demanding deep learning (DL) tasks while meeting the deadlines of time-sensitive applications. However, FPGAs require reconfiguration to execute different tasks. In this paper, we first demonstrate that FPGAs can be reconfigured in real-time. Additionally, we propose ELEVATE as a novel scheduling algorithm for reconfigurable heterogeneous edge computing platforms targeting Industry 4.0 post-production quality control. ELEVATE design focusses on optimising the reconfiguration of the FPGA unit for heterogeneous quality inspection tasks. Our simulations indicate that ELEVATE reduces task waiting time by up to two orders of magnitude and achieves energy savings of up to 25 % compared to a statically configured FPGA unit.
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Keywords
Edge computing , Heterogeneous compute nodes , ELEVATE , Field-programmable gate array (FPGA)
Citation
Hoyer, I., Zaarour, T., Khalid, A., Utz, A., Seidl, K., Brown, K. and Zahran, A. H. (2024) 'ELEVATE: Optimal scheduling of time-sensitive tasks on the heterogeneous reconfigurable Edge', 2024 IEEE 32nd International Conference on Network Protocols (ICNP), Charleroi, Belgium, 28-31 October 2024, pp. 1-6. https://doi.org/10.1109/ICNP61940.2024.10858561
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