High-performance building blocks for analogue-to-digital converters

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dc.check.date2029-05-31
dc.check.infoControlled Access
dc.contributor.advisorO'Hare, Daniel
dc.contributor.advisorMcCarthy, Kevin G.
dc.contributor.advisorO'Connell, Ivan
dc.contributor.authorChevella, Subhashen
dc.date.accessioned2026-01-26T11:52:29Z
dc.date.available2026-01-26T11:52:29Z
dc.date.issued2025
dc.date.submitted2025
dc.descriptionControlled Access
dc.description.abstractThis thesis presents circuit implementation techniques aimed at enhancing the performance of analogue mixed-signal circuits. It is structured into three parts, each addressing specific performance improvements for different circuit architectures. The first part of the thesis discusses a technique for improving the energy efficiency of comparators for ultra-low-power applications. The prototype is designed in a 65 nm CMOS process and the measurement results have demonstrated a 30% reduction in power consumption while maintaining similar input-referred noise levels compared to the widely used conventional double-tail latch type comparator. Furthermore, the proposed technique proves to be an excellent choice for compact area applications, making it highly suitable for energy-efficient circuit designs. The second part of the thesis presents techniques and architectural modifications in noise-shaping successive approximation register (SAR) analogue-to-digital converters (ADC). The technique utilizes an error-feedback topology to build a more robust noise-shaping loop filter without integrators. Furthermore, novel cascade of dynamic amplifiers architecture is used to avoid the series switches on top-plate capacitor node of a SAR ADC. The prototype is designed in a 28 nm CMOS process and the measurements have demonstrated that the proposed architecture achieves improved performance with SNDR and SFDR of 78.5 dB and 82.9 dB respectively. Lastly, the final part of the thesis presents a technique to extend the bandwidth of an open-loop Voltage Controlled Oscillator (VCO) based ADC, using the Time Interleaving (TI) principle. Unlike the conventional TI implementation, the presented concept uses a single VCO channel and interleaves the sampling circuits. This approach utilizes the wide VCO bandwidth and operates effectively at a higher sampling rate compared to traditional implementations. Furthermore, the proposed design overcomes the speed constraints imposed by the technology, achieving enhanced performance with minimal additional hardware, resulting a highly compact solution. The post-layout extracted simulation results demonstrate that, for a 230 MHz bandwidth, the proposed open-loop interleaved VCO-based ADC achieves an SNR of 39.96 dB, compared to 27.33 dB in the conventional open-loop implementation.en
dc.description.statusNot peer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationChevella, S. 2025. High-performance building blocks for analogue-to-digital converters. PhD Thesis, University College Cork.
dc.identifier.endpage176
dc.identifier.urihttps://hdl.handle.net/10468/18464
dc.language.isoenen
dc.publisherUniversity College Corken
dc.rights© 2025, Subhash Chevella.
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.subjectComparators
dc.subjectAnalogue-to-digital converters
dc.subjectSAR AC
dc.subjectVCO-based ADC
dc.subjectNoise-shaping
dc.titleHigh-performance building blocks for analogue-to-digital converters
dc.typeDoctoral thesisen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD - Doctor of Philosophyen
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