Cryo-CMOS modelling and calibration at 4 Kelvin: tools, methods, and applications

Montanares Sepúlveda, Mauricio

Cryo-CMOS modelling and calibration at 4 Kelvin: tools, methods, and applications

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Date

2025

Authors

Montanares Sepúlveda, Mauricio

Publisher

University College Cork

Abstract

Quantum computing has become increasingly significant due to its potential to efficiently address complex problems that classical computing struggles to solve. A primary obstacle to practical quantum computing implementations is the scalable integration and precise control of numerous quantum bits (qubits). Solid-state qubits, such as spin-based and superconducting types, require milli-Kelvin temperatures to maintain quantum coherence and proper operation. Current qubit-control methodologies employing room-temperature electronics introduce considerable thermal loads and wiring complexity, limiting scalability. Cryogenic CMOS (Cryo-CMOS), which utilises standard CMOS technology operating at 4 K—near qubit temperatures—represents a promising solution to these challenges. Nonetheless, standard Process Design Kits (PDKs), calibrated for conventional temperature ranges (–55 °C to 125 °C), fail to accurately capture significant changes in semiconductor behaviour under cryogenic conditions, including increased threshold voltages, enhanced carrier mobility, and altered subthreshold characteristics. The successful implementation of Cryo-CMOS controllers thus relies on precise cryogenic device modelling and calibration techniques. Although commercial PDK-calibration tools exist, they are typically expensive, with essential modules for advanced scripting or optimisation methods sold separately at similarly elevated cost, require significant manual intervention, often offer limited flexibility, and are not optimised for cryogenic applications, making them prohibitive for small research groups. To overcome these limitations and support precise cryogenic device calibration, a 65 nm chip containing some stand-alone transistor structures, previously fabricated by the Cryo-CMOS group at MCCI, was measured at both room temperature and 4 K to capture the I–V characteristics required for calibration. Building on these measurements, the first key contribution of this thesis is IceMOS, a Python-based tool developed to automate several recursive calibration tasks. IceMOS uses experimental I–V curves measured at both temperatures into the BSIM4 device model and generates all required spice simulation netlists. The user then iteratively adjusts selected model parameters, observing simulated curves alongside laboratory measurements until the error is minimised. IceMOS also automates device-model extraction, formats measurement data into CSV for streamlined comparison, and exports calibrated parameters fully compatible with standard PDKs. By significantly reducing manual effort and computational time, IceMOS enables faster and more efficient calibration of cryogenic CMOS models, achieving median errors below 5\% for PMOS and NMOS devices operating in the strong-inversion region. Following standard calibration methodologies reported in the literature, where comprehensive characterisation across all device bins is required, a second 65 nm chip was subsequently designed and fabricated. This chip includes a complete set of transistor bins, along with a simple amplifier structure. As a second contribution, this thesis also presents testing results obtained from this new chip under cryogenic conditions. In both the literature and the IceMOS calibration flow, parameters such as threshold voltage and slope factor are often initially estimated, a practice that can introduce significant inaccuracies. A third contribution of this thesis is the application of the S-EKV model combined with a Z-score filtering technique to systematically obtain precise initial values for these critical parameters, thus eliminating the reliance on estimations. This filtering approach was particularly important when addressing measurement-quality challenges at 4 K, where noise in the subthreshold and transition regions can significantly impact parameter extraction. The Z-score algorithm effectively removed outliers from the raw measurement data, reducing extraction errors from above 10\% to under 2\%, and significantly improving the reliability of the calibrated models. By first obtaining accurate S-EKV parameters and then using them as starting points for BSIM4 calibration, the methodology achieved excellent results with both the commercial 65 nm node and the open-source Sky130 130 nm technology, the latter leveraging publicly available datasets. The practical effectiveness of both IceMOS and the Z-score filtering technique has been demonstrated through experimental validation and reported in peer-reviewed IEEE conference publications. Overall, this thesis represents foundational work, presenting robust methodologies, thorough documentation, and practical tools designed to significantly advance research and development in Cryo-CMOS technology.

Description

Controlled Access

Keywords

Cryo-CMOS , Microelectronics , Modelling

Citation

Montanares Sepúlveda, M. 2025. Cryo-CMOS modelling and calibration at 4 Kelvin: tools, methods, and applications. MRes Thesis, University College Cork.