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Gate driver systems using heterogeneously integrated transformers for isolated signal and power transfer
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Date
2025
Authors
O'Sullivan, Brendan C.
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University College Cork
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Abstract
This thesis investigates gate driver design for advanced highly integrated power systems, specifically for the next generation of 48 V to Point of Load (POL) converters (1 V - 1.8 V) for server computing. The ever-increasing energy demands of artificial intelligence is driving chip power consumption well above 1 kW, thus resulting in significant currents (1.4 kA+), which is driving the design of high current power converters towards multi-stage, multi-phase, and multi-level designs, which feature significantly more floating low-voltage switches, all of which require a highly integrated galvanically isolated gate driver, particularly when considered in the context of the trend for vertical power or direct-to-chip converters.
A custom thin-film, magnetics-on-silicon 1:1, 32 nH solenoid transformer was fabricated by the Tyndall National Institute as part of this research. The device was fabricated using a CMOS Back End of Line (BEOL) compatible process, enabling monolithic or heterogeneous integration of the gate driver transformer with the gate driver circuits developed for this work and investigated for both isolated signal transfer and gate driver powering. The transformer enables 5 kV of functional isolation of the gate driver, as well as low input-output capacitance, CIO. This is important for transferring digital drive signals and power to isolated floating high speed power switches, in a variety of technologies, such as LDMOS, VDMOS, GaN d-HEMT, GaN e-HEMT, and SiC MOSFET. High frequency operation and fast switching speeds are required and thus the gate driver loop was investigated for the parasitic components within the loop which limit the rise and fall times of the gate voltage. Coarse geometry integration of the driver and power switches results in problematic higher gate driving and shared source parasitic inductances. Methods to characterize a new custom IHP SG130 nm BiCMOS gate driving IC and a new custom fabricated 25 V monolithic asymmetrical GaN d-HEMT switching bridge system were explored, to understand the impacts of these interconnect parasitic inductances.
The design of the signal-isolating gate driver system centred on a very low volt-seconds differential pulse drive scheme to enable the use of the 32 nH custom thin-film transformer. It included the design of the custom prototype IHP SG130 nm CMOS gate-driver signal-coupling chipset, which achieved operation with 4.3 V.ns gate driver signal pulses, and a simulated common-mode transient immunity (CMTI) of 34 V/ns. Simulations on a further improved design, with balanced impedances, achieved a CMTI of 200 V/ns. To extend from this signal coupling system, with this miniature transformer, an isolated bias supply was designed. A half-bridge LLC resonant bias converter with voltage-doubler output was chosen as this topology halves the applied volt-seconds and therefore is suitable for the thin-film transformer. The converter design was optimised for the case of a 180 nm monolithic gate-driver bias converter and was prototyped using equivalent GaN e-HEMT power switches. A new alternating inverted burst mode (AIBM) drive scheme was proposed, designed, and tested, featuring an even number of pulses with half-width pulses for both burst entry and exit. This burst mode was determined to provide advantages over the state-of-the-art systems which have an odd number of pulses per burst and exit each burst with a full width pulse. The prototype system achieved over 58% efficiency at 700 mW in continuous mode and improves the burst mode efficiency by 4% in comparison with previous burst schemes.
In summary, this research focuses on the impacts of parasitic inductances in the gate driver loop, in the context of gate driver implementations with deep heterogenous or monolithic integration. It has proposed an isolated gate driver solution consisting of signal and power transfer circuits which are applicable to low magnetizing inductance transformers, such as substrate-embeddable or thin-film transformers, which have orders of magnitude lower magnetising inductances than normal, but which are amenable to high levels of miniaturisation and integration. As such, it is feasible to realize highly integrated gate drivers which are suitable for high-frequency, multi-level, multi-phase topologies, in applications such as 48 V to POL or Intermediate Bus Converters (IBC) to solve the exponentially growing power distribution challenges in applications such as server power cards for AI datacentres.
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Keywords
Isolated gate driver , 48 V to POL converters , 180 nm CMOS , LLC converters , Thin-film magnetics , CoZrTaB , PwrSiP , PwrSoC , Functional isolation , 200 V/ns CMTI , Heterogeneous integration
Citation
O'Sullivan, B. C. 2025. Gate driver systems using heterogeneously integrated transformers for isolated signal and power transfer. PhD Thesis, University College Cork.