Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysis

dc.check.date2019-03-21
dc.check.infoAccess to this article is restricted until 12 months after publication by request of the publisher.en
dc.contributor.authorKhosravi, Ava
dc.contributor.authorAzcatl, Angelica
dc.contributor.authorBolshakov, Pavel
dc.contributor.authorMirabelli, Gioele
dc.contributor.authorZhao, Peng
dc.contributor.authorCaruso, Enrico
dc.contributor.authorHinkle, Christopher L.
dc.contributor.authorHurley, Paul K.
dc.contributor.authorWallace, Robert M.
dc.contributor.authorYoung, Chadwin D.
dc.contributor.funderScience Foundation Irelanden
dc.contributor.funderNational Science Foundationen
dc.date.accessioned2018-03-26T11:19:20Z
dc.date.available2018-03-26T11:19:20Z
dc.date.issued2018
dc.date.updated2018-03-21T11:22:35Z
dc.description.abstractAbstract Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C-V characterization. Frequency dependent C-V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices.The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C-V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps.en
dc.description.sponsorshipNational Science Foundation (NSF-ECCS–1407765)en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.articleid031002
dc.identifier.citationZhao, P., Khosravi, A., Azcatl, A., Bolshakov, P., Mirabelli, G., Caruso, E., Hinkle, C. L., Hurley, P. K ., Wallace, R. M., Young, C. D. (2018) 'Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysis', 2D Materials, 5(3), 031002 (8pp). doi:10.1088/2053-1583/aab728en
dc.identifier.doi10.1088/2053-1583/aab728
dc.identifier.endpage8
dc.identifier.issn2053-1583
dc.identifier.issued3
dc.identifier.journaltitle2D Materialsen
dc.identifier.startpage1
dc.identifier.urihttps://hdl.handle.net/10468/5692
dc.identifier.volume5
dc.language.isoenen
dc.publisherIOP Publishing Ltd.en
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI US Ireland R&D Partnership/13/US/I2862/IE/Understanding the Nature of Interfaces in Two Dimensional Electronic Devises (UNITE)/en
dc.rights© 2018, IOP Publishing Ltd. This Accepted Manuscript is available for reuse under a CC BY-NC-ND 3.0 licence.en
dc.rights.urihttps://creativecommons.org/licences/by-nc-nd/3.0en
dc.subjectTransition metal dichalcogenidesen
dc.subjectTMDsen
dc.subjectBorder trapsen
dc.subjectInterface trapsen
dc.subjectHfO2 / MoS2en
dc.subjectCapacitance - voltageen
dc.subjectC-Ven
dc.titleEvaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysisen
dc.typeArticle (peer-reviewed)en
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