Hardware processors for pairing-based cryptography

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dc.check.embargoformatNot applicableen
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dc.check.opt-outNot applicableen
dc.check.reasonNo embargo requireden
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dc.contributor.advisorMurphy, Colinen
dc.contributor.authorRonan, Robert
dc.date.accessioned2016-11-18T11:32:55Z
dc.date.available2016-11-18T11:32:55Z
dc.date.issued2016
dc.date.submitted2016
dc.description.abstractBilinear pairings can be used to construct cryptographic systems with very desirable properties. A pairing performs a mapping on members of groups on elliptic and genus 2 hyperelliptic curves to an extension of the finite field on which the curves are defined. The finite fields must, however, be large to ensure adequate security. The complicated group structure of the curves and the expensive field operations result in time consuming computations that are an impediment to the practicality of pairing-based systems. The Tate pairing can be computed efficiently using the ɳT method. Hardware architectures can be used to accelerate the required operations by exploiting the parallelism inherent to the algorithmic and finite field calculations. The Tate pairing can be performed on elliptic curves of characteristic 2 and 3 and on genus 2 hyperelliptic curves of characteristic 2. Curve selection is dependent on several factors including desired computational speed, the area constraints of the target device and the required security level. In this thesis, custom hardware processors for the acceleration of the Tate pairing are presented and implemented on an FPGA. The underlying hardware architectures are designed with care to exploit available parallelism while ensuring resource efficiency. The characteristic 2 elliptic curve processor contains novel units that return a pairing result in a very low number of clock cycles. Despite the more complicated computational algorithm, the speed of the genus 2 processor is comparable. Pairing computation on each of these curves can be appealing in applications with various attributes. A flexible processor that can perform pairing computation on elliptic curves of characteristic 2 and 3 has also been designed. An integrated hardware/software design and verification environment has been developed. This system automates the procedures required for robust processor creation and enables the rapid provision of solutions for a wide range of cryptographic applications.en
dc.description.statusNot peer revieweden
dc.description.versionAccepted Version
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRonan, R. 2016. Hardware processors for pairing-based cryptography. PhD Thesis, University College Cork.en
dc.identifier.endpage265en
dc.identifier.urihttps://hdl.handle.net/10468/3291
dc.languageEnglishen
dc.language.isoenen
dc.publisherUniversity College Corken
dc.rights© 2016, Robert Ronan.en
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/en
dc.subjectCryptographyen
dc.subjectHardwareen
dc.subjectIdentity based encryptionen
dc.subjectSoftwareen
dc.subjectBilinear pairingsen
dc.subjectElliptic hyperelliptic curvesen
dc.subjectAutomation of design and verificationen
dc.thesis.opt-outfalse
dc.titleHardware processors for pairing-based cryptographyen
dc.typeDoctoral thesisen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePHD (Engineering)en
ucc.workflow.supervisorcmurphy@rennes.ucc.ie
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