Low power predictable memory and processing architectures

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dc.check.embargoformatE-thesis on CORA onlyen
dc.check.entireThesisEntire Thesis Restricteden
dc.check.opt-outNot applicableen
dc.check.reasonThis thesis is due for publication or the author is actively seeking to publish this materialen
dc.contributor.advisorPopovici, Emanuel M.en
dc.contributor.authorChen, Jiaoyan
dc.contributor.funderScience Foundation Irelanden
dc.date.accessioned2013-07-15T12:37:09Z
dc.date.available2014-07-16T04:00:06Z
dc.date.issued2013
dc.date.submitted2013
dc.description.abstractGreat demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally.en
dc.description.sponsorshipScience Foundation Ireland (07/IN.1/I977)en
dc.description.statusNot peer revieweden
dc.description.versionAccepted Version
dc.format.mimetypeapplication/pdfen
dc.identifier.citationChen, J. 2013. Low power predictable memory and processing architectures. PhD Thesis, University College Cork.en
dc.identifier.endpage125
dc.identifier.urihttps://hdl.handle.net/10468/1174
dc.language.isoenen
dc.publisherUniversity College Corken
dc.rights© 2013, Jiaoyan Chen.en
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/en
dc.subjectLow poweren
dc.subjectAdiabaticen
dc.subjectAsynchronousen
dc.subjectPredictableen
dc.subject.lcshElectric power--Conservationen
dc.subject.lcshElectric leakage--Preventionen
dc.subject.lcshMetal oxide semiconductors, Complementary--Design and constructionen
dc.subject.lcshElectronic digital computers--Power supplyen
dc.thesis.opt-outfalse*
dc.titleLow power predictable memory and processing architecturesen
dc.typeDoctoral thesisen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePHD (Engineering)en
ucc.workflow.supervisorcora@ucc.ie*
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