Electronic design automation methodologies for digital VLSI circuit reliability analysis and optimisation

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Yang, Bo
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University College Cork
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As the continuous scaling on both size and the operating voltage of the Very Large Scale Integrated (VLSI) circuits for improved power and area efficiencies, keeping the acceptable reliability has become an increasingly significant challenge of the digital circuits in addition to the power consumption and area. In this thesis, a number of modern Electronic Design Automation (EDA) algorithms and approaches emphasizing the digital circuit reliability analysis and optimisation were investigated. In this work, the reliability is categorized into two aspects, i.e., the reliability related to the soft error events in the circuit and the timing related reliability. In terms of the soft error events, an error may be injected into the circuit unexpectedly, which may eventually impact the correctness of the computation executed by the circuit. What makes the analysis complex is that when an error occurred somewhere in the circuit, the error may or may not propagate through the circuit and be reflected on the output due to the masking phenomena. Monte-Carlo (MC) simulation was the standard method to solve the problem in the traditional workflow until the circuit scale became sufficiently large that it is out of the tractable computation performance. Thus, analytical approaches for soft error propagation algorithms were under research for decades. In this work, a conditional probability based soft error propagation algorithm, CPEP, that can achieve significant performance boost compared to the MC simulation, while maintaining high accuracy was developed. In addition, building on the foundation of the CPEP reliability analysis algorithm, a complete EDA framework to enhance the reliability during the circuit synthesis was proposed. The timing related reliability is a measure of the probabilities that the circuit outputs can properly switch to the desired voltage level at a certain delay (i.e., Cut-off delay). The analysis of this kind of reliability is a process of Statistical Static Timing Analysis (SSTA), which has become a very active research area in the last decades. In our work, the Artificial Neural Network (ANN) function approximator based SSTA gate models for accurate and fast estimation of the propagation delay, Tpd, distribution (hence the reliability) was explored. All these methods for reliability analysis are fully compatible with existing electronics design flows using classical Boolean circuit synthesis methods. In the quest to design reliable, efficient circuits, alternative circuit architectures were investigated, which may not follow the classical CMOS design flow. ANNs are such architectures that promise more efficient implementations of digital circuits and can be a viable alternative to the current CMOS-based VLSI circuit architectures. A synthesis framework for Multilayer Perceptron (MLP) based Boolean logic gates was investigated. Experimental results show that with this architecture, the logic circuit can be implemented effectively, resulting in smaller propagation delay and also the more predictable variations. A typical Boolean circuit consists of many types of gates. Implementing the linear circuits (i.e., XOR networks) is particularly difficult for an MLP Boolean function approximator. Thus, a circuit linearization framework based on Boolean function Bi-decomposition was proposed to separate the linear part from the non-linear part (composed of the rest of gate types). Then, an MLP-based circuit can be used to implement the non-linear part more effectively while the linear part can be part of an error control coding scheme, which can further improve circuit reliability.
Very large scale integrated circuit (VLSI) , Electronic design automation (EDA) , Digital reliability and optimisation , Statistical static timing analysis (SSTA) , Soft error propagation , MLP based logic circuit
Yang, B. 2020. Electronic design automation methodologies for digital VLSI circuit reliability analysis and optimisation. PhD Thesis, University College Cork.