Low power predictable memory and processing architectures

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dc.contributor.advisor Popovici, Emanuel M. en
dc.contributor.author Chen, Jiaoyan
dc.date.accessioned 2013-07-15T12:37:09Z
dc.date.available 2014-07-16T04:00:06Z
dc.date.issued 2013
dc.date.submitted 2013
dc.identifier.citation Chen, J. 2013. Low power predictable memory and processing architectures. PhD Thesis, University College Cork. en
dc.identifier.endpage 125
dc.identifier.uri http://hdl.handle.net/10468/1174
dc.description.abstract Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally. en
dc.description.sponsorship Science Foundation Ireland (07/IN.1/I977) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2013, Jiaoyan Chen. en
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/ en
dc.subject Low power en
dc.subject Adiabatic en
dc.subject Asynchronous en
dc.subject Predictable en
dc.subject.lcsh Electric power--Conservation en
dc.subject.lcsh Electric leakage--Prevention en
dc.subject.lcsh Metal oxide semiconductors, Complementary--Design and construction en
dc.subject.lcsh Electronic digital computers--Power supply en
dc.title Low power predictable memory and processing architectures en
dc.type Doctoral thesis en
dc.type.qualificationlevel Doctoral en
dc.type.qualificationname PHD (Engineering) en
dc.internal.availability Full text available en
dc.description.version Accepted Version
dc.contributor.funder Science Foundation Ireland en
dc.description.status Not peer reviewed en
dc.internal.school Electrical and Electronic Engineering en
dc.check.reason This thesis is due for publication or the author is actively seeking to publish this material en
dc.check.opt-out Not applicable en
dc.thesis.opt-out false *
dc.check.entireThesis Entire Thesis Restricted en
dc.check.embargoformat E-thesis on CORA only en
ucc.workflow.supervisor cora@ucc.ie *


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© 2013, Jiaoyan Chen. Except where otherwise noted, this item's license is described as © 2013, Jiaoyan Chen.
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