Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources

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dc.contributor.advisor O'Hare, Daniel en
dc.contributor.advisor O'Connell, Ivan en
dc.contributor.author Zheng, Hao
dc.date.accessioned 2022-01-26T15:35:50Z
dc.date.available 2022-01-26T15:35:50Z
dc.date.issued 2021-06
dc.date.submitted 2021-06
dc.identifier.citation Zheng, H. 2021. Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources. MRes Thesis, University College Cork. en
dc.identifier.endpage 144 en
dc.identifier.uri http://hdl.handle.net/10468/12483
dc.description.abstract This thesis clarifies a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. This correction scheme has reduced the side band noise in the output signal and allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits. When slope and double slope ADCs with 6 bits of resolution are selected the scheme can be implemented consuming up to additional power consumption of 6.8mW. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher University College Cork en
dc.rights © 2021, Hao Zheng. en
dc.rights.uri https://creativecommons.org/licenses/by-sa/4.0/ en
dc.subject Mixed signal compensation en
dc.subject DPLL clock sources en
dc.subject Sampling errors in ADCs en
dc.title Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources en
dc.type Masters thesis (Research) en
dc.type.qualificationlevel Masters en
dc.type.qualificationname MRes - Master of Research en
dc.internal.availability Full text not available en
dc.description.version Accepted Version en
dc.description.status Not peer reviewed en
dc.internal.school Process and Chemical Engineering en
dc.internal.conferring Spring 2022 en
dc.internal.ricu Tyndall National Institute en
dc.availability.bitstream embargoed
dc.check.date 2025-05-30

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© 2021, Hao Zheng. Except where otherwise noted, this item's license is described as © 2021, Hao Zheng.
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