Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysis
Khosravi, Ava; Azcatl, Angelica; Bolshakov, Pavel; Mirabelli, Gioele; Zhao, Peng; Caruso, Enrico; Hinkle, Christopher L.; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.
Date:
2018
Copyright:
© 2018, IOP Publishing Ltd. This Accepted Manuscript is available for reuse under a CC BY-NC-ND 3.0 licence.
Full text restriction information:
Access to this article is restricted until 12 months after publication by request of the publisher.
Restriction lift date:
2019-03-21
Citation:
Zhao, P., Khosravi, A., Azcatl, A., Bolshakov, P., Mirabelli, G., Caruso, E., Hinkle, C. L., Hurley, P. K ., Wallace, R. M., Young, C. D. (2018) 'Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysis', 2D Materials, 5(3), 031002 (8pp). doi:10.1088/2053-1583/aab728
Abstract:
Abstract Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C-V characterization. Frequency dependent C-V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices.The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C-V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps.
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Except where otherwise noted, this item's license is described as © 2018, IOP Publishing Ltd. This Accepted Manuscript is available for reuse under a CC BY-NC-ND 3.0 licence.