Access to this article is restricted until 24 months after publication by request of the publisher.. Restriction lift date: 2020-08-04
Effect of strain and diameter on electronic and charge transport properties of indium arsenide nanowires
No Thumbnail Available
Files
Accepted version
Date
2018-08-04
Authors
Razavi, Pedram
Greer, James C.
Journal Title
Journal ISSN
Volume Title
Publisher
Elsevier
Published Version
Abstract
The impact of uni-axial compressive and tensile strain and diameter on the electronic band structure of indium arsenide (InAs) nanowires (NWs) is investigated using first principles calculations. Effective masses and band gaps are extracted from the electronic structure for relaxed and strained nanowires. Material properties are extracted and applied to determine charge transport through the NWs described within the effective mass approximation and by applying the non-equilibrium Green’s function method. The transport calculations self-consistently solve the Schrödinger equation with open boundary conditions and Poisson’s equation for the electrostatics. The device structure corresponds to a metal oxide semiconductor field effect transistor (MOSFET) with an InAs NW channel in a gate-all-around geometry. The channel cross sections are for highly scaled devices within a range of 3 × 3–1 × 1 nm2. Strain effects on the band structures and electrical performance are evaluated for different NW orientations and diameters by quantifying subthreshold swing and ON/OFF current ratio. Our results reveal for InAs NW transistors with critical dimensions of a few nanometer, the crystallographic orientation and quantum confinement effects dominate device behavior, nonetheless strain effects must be included to provide accurate predictions of transistor performance.
Description
Keywords
InAs nanowires , Strain , Charge transport , Semiconductors , DFT , Meta-GGA
Citation
Razavi, P. and Greer, J. C. (2018) 'Effect of strain and diameter on electronic and charge transport properties of indium arsenide nanowires', Solid-State Electronics, 149, pp. 6-14. doi: 10.1016/j.sse.2018.08.001