The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices

Simple item page
dc.contributor.authorGammon, P. M.
dc.contributor.authorLi, F.
dc.contributor.authorChan, C. W.
dc.contributor.authorSanchez, A.
dc.contributor.authorHindmarsh, S.
dc.contributor.authorGity, Farzan
dc.contributor.authorTrajkovic, T.
dc.contributor.authorKilchytska, V.
dc.contributor.authorPathirana, V.
dc.contributor.authorCamuso, G.
dc.contributor.authorBen Ali, K.
dc.contributor.authorFlandre, Denis
dc.contributor.authorMawby, P. A.
dc.contributor.authorGardner, J. W.
dc.contributor.funderHorizon 2020
dc.contributor.funderRoyal Academy of Engineering
dc.contributor.funderEngineering and Physical Sciences Research Council
dc.date.accessioned2018-07-30T12:30:36Z
dc.date.available2018-07-30T12:30:36Z
dc.date.issued2017
dc.description.abstractA new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationP. M. Gammon et al. (2017) ‘The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices’, Materials Science Forum, 897, pp. 747-750. doi: 10.4028/www.scientific.net/MSF.897.747en
dc.identifier.doi10.4028/www.scientific.net/MSF.897.747
dc.identifier.endpage750
dc.identifier.issn0255-5476
dc.identifier.issn1662-9752
dc.identifier.journaltitleMaterials Science Forumen
dc.identifier.startpage747
dc.identifier.urihttps://hdl.handle.net/10468/6548
dc.identifier.volume897
dc.language.isoenen
dc.publisherTrans Tech Publications Ltden
dc.relation.projectinfo:eu-repo/grantAgreement/EC/H2020::RIA/687361/EU/Si on SiC for the Harsh Environment of Space/SaSHa
dc.relation.projectinfo:eu-repo/grantAgreement/RCUK/EPSRC/EP/N00647X/1/GB/Silicon-Silicon Carbide (Si/SiC) Power Devices for high temperature, hostile environment applications/
dc.rights© 2017, Trans Tech Publications Inc. All rights reserved.en
dc.subjectHarsh environmenten
dc.subjectLateral MOSFETen
dc.subjectSiliconen
dc.subjectSilicon carbideen
dc.subjectSiCen
dc.subjectWafer bondingen
dc.titleThe effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devicesen
dc.typeArticle (peer-reviewed)en
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
WRAP-effect-interfacial-charge-development-wafer-bonded-Gammon-2017.pdf
Size:
706.99 KB
Format:
Adobe Portable Document Format
Description:
Accepted Version
Download
Collections
Tyndall National Institute - Journal Articles