Cryptographic coprocessors for embedded systems

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dc.check.embargoformatNot applicableen
dc.check.infoNo embargo requireden
dc.check.opt-outNot applicableen
dc.check.reasonNo embargo requireden
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dc.contributor.advisorMarnane, William P.en
dc.contributor.authorHamilton, Mark
dc.contributor.funderScience Foundation Irelanden
dc.date.accessioned2015-01-26T10:09:30Z
dc.date.available2015-01-26T10:09:30Z
dc.date.issued2014
dc.date.submitted2014
dc.description.abstractIn the field of embedded systems design, coprocessors play an important role as a component to increase performance. Many embedded systems are built around a small General Purpose Processor (GPP). If the GPP cannot meet the performance requirements for a certain operation, a coprocessor can be included in the design. The GPP can then offload the computationally intensive operation to the coprocessor; thus increasing the performance of the overall system. A common application of coprocessors is the acceleration of cryptographic algorithms. The work presented in this thesis discusses coprocessor architectures for various cryptographic algorithms that are found in many cryptographic protocols. Their performance is then analysed on a Field Programmable Gate Array (FPGA) platform. Firstly, the acceleration of Elliptic Curve Cryptography (ECC) algorithms is investigated through the use of instruction set extension of a GPP. The performance of these algorithms in a full hardware implementation is then investigated, and an architecture for the acceleration the ECC based digital signature algorithm is developed. Hash functions are also an important component of a cryptographic system. The FPGA implementation of recent hash function designs from the SHA-3 competition are discussed and a fair comparison methodology for hash functions presented. Many cryptographic protocols involve the generation of random data, for keys or nonces. This requires a True Random Number Generator (TRNG) to be present in the system. Various TRNG designs are discussed and a secure implementation, including post-processing and failure detection, is introduced. Finally, a coprocessor for the acceleration of operations at the protocol level will be discussed, where, a novel aspect of the design is the secure method in which private-key data is handleden
dc.description.sponsorshipScience Foundation Ireland (SFI Grant 06/MI/006)en
dc.description.statusNot peer revieweden
dc.description.versionAccepted Version
dc.format.mimetypeapplication/pdfen
dc.identifier.citationHamilton, M. 2014. Cryptographic coprocessors for embedded systems. PhD Thesis, University College Cork.en
dc.identifier.endpage174
dc.identifier.urihttps://hdl.handle.net/10468/1770
dc.language.isoenen
dc.publisherUniversity College Corken
dc.rights© 2014, Mark Hamiltonen
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/en
dc.subjectFPGAen
dc.subjectElliptic curve cryptography (ECC)en
dc.subjectTRNGen
dc.subjectHash functionsen
dc.subjectAESen
dc.subjectSSL/TLSen
dc.subjectCryptographyen
dc.thesis.opt-outfalse
dc.titleCryptographic coprocessors for embedded systemsen
dc.typeDoctoral thesisen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePHD (Engineering)en
ucc.workflow.supervisorl.marnane@ucc.ie
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