4.48-GHz fractional- N frequency synthesizer with spurious-tone suppression via probability mass redistribution

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dc.contributor.authorDonnelly, Yann
dc.contributor.authorKennedy, Michael Peter
dc.contributor.authorBreslin, James
dc.contributor.authorTulisi, Stefano
dc.contributor.authorSanganagouda, Patil
dc.contributor.authorCurtin, Ciarán
dc.contributor.authorBrookes, Stephen
dc.contributor.authorShelly, Brian
dc.contributor.authorGriffin, Patrick
dc.contributor.authorKeaveney, Michael
dc.date.accessioned2020-02-19T16:48:18Z
dc.date.available2020-02-19T16:48:18Z
dc.date.issued2019-09-26
dc.description.abstractA 4.48-GHz type-II charge pump fractional-N PLL implemented in a 0.18-μm BiCMOS process is presented. The divider controller's output is processed using a novel block, the probability mass redistributor, which statistically reconfigures the modulation noise such that fractional spurs are minimized. Measurements demonstrate in-band fractional spurs of -80 dBc. The solution, which is a drop-in modification of a conventional MASH structure, incurs a modulator area increase of 22%, and can be used in conjunction with other linearization strategies.en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationDonnelly, Y., Kennedy, M. P., Breslin, J., Tulisi, S., Patil, S., Curtin, C., Brookes, S., Shelly, B., Griffin, P. and Keaveney, M. (2019) '4.48-GHz Fractional- N Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass Redistribution', IEEE Solid-State Circuits Letters, 2(11), pp. 264-267. doi: 10.1109/LSSC.2019.2943936en
dc.identifier.doi10.1109/LSSC.2019.2943936en
dc.identifier.endpage267en
dc.identifier.issn2573-9603
dc.identifier.issued11en
dc.identifier.journaltitleIEEE Solid-State Circuits Letteren
dc.identifier.startpage264en
dc.identifier.urihttps://hdl.handle.net/10468/9672
dc.identifier.volume2en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.urihttps://ieeexplore.ieee.org/document/8850113
dc.rights© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.subjectBiCMOSen
dc.subjectDigital delta–sigma modulationen
dc.subjectFrequency synthesisen
dc.subjectPhase-lock loopen
dc.subjectSpursen
dc.subjectMulti-stage noise shapingen
dc.subjectFrequency synthesizersen
dc.subjectPhase locked loopsen
dc.subjectFrequency modulationen
dc.subjectSolid state circuitsen
dc.subjectPhase modulationen
dc.title4.48-GHz fractional- N frequency synthesizer with spurious-tone suppression via probability mass redistributionen
dc.typeArticle (peer-reviewed)en
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