A systematic review of blockchain hardware acceleration architectures

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dc.contributor.authorO'Mahony, Aidan T.
dc.contributor.authorPopovici, Emanuel M.
dc.contributor.funderIntel Corporationen
dc.contributor.funderScience Foundation Irelanden
dc.date.accessioned2019-10-01T11:17:32Z
dc.date.available2019-10-01T11:17:32Z
dc.date.issued2019-06
dc.date.updated2019-10-01T11:04:42Z
dc.description.abstractThe aim of this paper is to provide a systematic literature review of blockchain hardware acceleration. Blockchain technology has achieved significant attention in recent years particularly in the area of cryptocurrency however it is gaining popularity in other applications such as supply chain management and e-government. Based on a structured, systematic review of the relevant literature, we present a classification of the primary areas in blockchain technology that make use of heterogeneous hardware for accelerating certain blockchain functions. Based on these findings, we identify various research gaps and future exploratory directions that are anticipated to be of significant value both for academics and industry practitioners.en
dc.description.sponsorshipIntel Corporation (Intel Programmable Solutions Group);en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationO'Mahony, A. and Popovici, E. (2019) 'A Systematic Review of Blockchain Hardware Acceleration Architectures', 30th Irish Signals and Systems Conference (ISSC 2019) Maynooth, Ireland, 17-18 June. doi: 10.1109/ISSC.2019.8904936en
dc.identifier.doi10.1109/ISSC.2019.8904936
dc.identifier.endpage6en
dc.identifier.isbn978-1-7281-2800-9
dc.identifier.startpage1en
dc.identifier.urihttps://hdl.handle.net/10468/8655
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI Research Centres/12/RC/2289/IE/INSIGHT - Irelands Big Data and Analytics Research Centre/en
dc.relation.urihttps://ieeexplore.ieee.org/document/8904936
dc.rights© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.subjectBlockchainen
dc.subjectDistributed ledger technologyen
dc.subjectHardware architectureen
dc.subjectSystematic literature reviewen
dc.subjectConsensus algorithmsen
dc.subjectHeterogeneous hardwareen
dc.subjectFPGAen
dc.subjectGPUen
dc.subjectASICen
dc.subjectCPUen
dc.titleA systematic review of blockchain hardware acceleration architecturesen
dc.typeConference itemen
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