Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s
| dc.availability.bitstream | openaccess | |
| dc.contributor.advisor | McCarthy, Kevin G. | en |
| dc.contributor.author | O'Sullivan, Gerald | |
| dc.date.accessioned | 2020-09-30T10:54:11Z | |
| dc.date.available | 2020-09-30T10:54:11Z | |
| dc.date.issued | 2020-07-10 | |
| dc.date.submitted | 2020-07-10 | |
| dc.description.abstract | The work in this thesis is based on the investigation and design of key circuit blocks in a high speed, high resolution SAR ADC in TSMC’s 28nm technology. The research carried out analyses the circuit limitations of the switched capacitor DAC and the settling problems of the reference voltage associated with a switched capacitor scheme. The switched capacitor DAC is a critical block for overall ADC performance and various trade-offs are weighed up before discussing the layout of the split capacitor DAC implemented in the project, from unit capacitor up to top level routing. It also investigates the main sources of error using this topology and implements effective ways of mitigating these errors. The schematic design of DAC switches is also carried out and the results section discusses the top level linearity performance of the DAC. This work also focuses on detailed analysis and implementation of a reference buffer circuit solution that is capable of supplying a reference voltage that is highly accurate and can settle in enough time for the high speed and high resolution specifications required by the SAR ADC. Various solutions were comprehensively investigated for this problem and the design of the chosen flipped voltage follower topology was implemented in schematic and layout. It was subsequently simulated at schematic and extracted parasitics level to verify its functionality and determine its overall performance. Finally, the work done in each block is verified in the context of the whole ADC by top level schematic and extracted layout simulation. | en |
| dc.description.status | Not peer reviewed | en |
| dc.description.version | Accepted Version | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | O'Sullivan, G. 2020. Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s. MRes Thesis, University College Cork. | en |
| dc.identifier.endpage | 122 | en |
| dc.identifier.uri | https://hdl.handle.net/10468/10609 | |
| dc.language.iso | en | en |
| dc.publisher | University College Cork | en |
| dc.rights | © 2020, Gerald O'Sullivan. | en |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/4.0/ | en |
| dc.subject | Microelectronics | en |
| dc.subject | Analogue electronics | en |
| dc.subject | Data conversion | en |
| dc.title | Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s | en |
| dc.type | Masters thesis (Research) | en |
| dc.type.qualificationlevel | Masters | en |
| dc.type.qualificationname | MSc - Master of Science | en |
