Reduced electric field in junctionless transistors
dc.contributor.author | Colinge, Jean-Pierre | |
dc.contributor.author | Lee, Chi-Woo | |
dc.contributor.author | Ferain, Isabelle | |
dc.contributor.author | Akhavan, Nima Dehdashti | |
dc.contributor.author | Yan, Ran | |
dc.contributor.author | Razavi, Pedram | |
dc.contributor.author | Yu, Ran | |
dc.contributor.author | Nazarov, Alexei N. | |
dc.contributor.author | Doria, Rodrigo T. | |
dc.contributor.funder | Science Foundation Ireland | |
dc.contributor.funder | Seventh Framework Programme | |
dc.date.accessioned | 2017-07-28T11:22:09Z | |
dc.date.available | 2017-07-28T11:22:09Z | |
dc.date.issued | 2010 | |
dc.description.abstract | The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present. (C) 2010 American Institute of Physics. (doi:10.1063/1.3299014) | en |
dc.description.sponsorship | Science Foundation Ireland (Grant Np. 05/IN/I888) | en |
dc.description.status | Peer reviewed | en |
dc.description.version | Published Version | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.articleid | 73510 | |
dc.identifier.citation | Colinge, J.-P., Lee, C.-W., Ferain, I., Akhavan, N. D., Yan, R., Razavi, P., Yu, R., Nazarov, A. N. and Doria, R. T. (2010) 'Reduced electric field in junctionless transistors', Applied Physics Letters, 96(7), pp. 073510. doi: 10.1063/1.3299014 | en |
dc.identifier.doi | 10.1063/1.3299014 | |
dc.identifier.endpage | 3 | |
dc.identifier.issn | 0003-6951 | |
dc.identifier.issn | 1077-3118 | |
dc.identifier.issued | 7 | |
dc.identifier.journaltitle | Applied Physics Letters | en |
dc.identifier.startpage | 1 | |
dc.identifier.uri | https://hdl.handle.net/10468/4346 | |
dc.identifier.volume | 96 | |
dc.language.iso | en | en |
dc.publisher | AIP Publishing | en |
dc.relation.project | info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/216171/EU/Silicon-based nanostructures and nanodevices for long term nanoelectronics applications/NANOSIL | |
dc.relation.project | info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/216373/EU/European platform for low-power applications on Silicon-on-Insulator Technology/EUROSOI+ | |
dc.relation.uri | http://aip.scitation.org/doi/abs/10.1063/1.3299014 | |
dc.rights | © 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Colinge, J.-P., Lee, C.-W., Ferain, I., Akhavan, N. D., Yan, R., Razavi, P., Yu, R., Nazarov, A. N. and Doria, R. T. (2010) 'Reduced electric field in junctionless transistors', Applied Physics Letters, 96(7), pp. 073510 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3299014 | en |
dc.subject | Trigate soi mosfets | en |
dc.subject | Inversion layer mobility | en |
dc.subject | Si mosfets | en |
dc.subject | Universality | en |
dc.subject | Silicon | en |
dc.subject | CMOS integrated circuits | en |
dc.subject | Electric fields | en |
dc.subject | Doping | en |
dc.subject | MOSFETs | en |
dc.subject | Carrier mobility | en |
dc.title | Reduced electric field in junctionless transistors | en |
dc.type | Article (peer-reviewed) | en |
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