Micro-transfer print integration of high-speed photodetectors to SOI platform
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Full Text E-thesis
Date
2024
Authors
Muthuganesan, Hemalatha
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Publisher
University College Cork
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Abstract
Photonic integrated circuits (PICs) offer a pivotal solution to meet the escalating demands of data bandwidth and used in data centres, LIDAR and optical sensing. Among various approaches, micro-transfer printing emerges as a rapid and universally compatible integration technology to generate PICs. To implement this technology, it is necessary to separate the devices from their original substrate using a release layer and transfer print them to designated location on target wafer. This enables the heterogeneous integration of numerous active devices from multiple wafers onto a single wafer, resulting in a compact and highly functional PIC. In addition to being a room temperature process, it is also cost-effective allowing reuse of expensive III-V substrates. This thesis demonstrates the application of micro-transfer printing technology in integrating ultra-thin, high-speed InGaAs photodetectors with silicon waveguides through various coupling mechanisms.
The thesis begins with optimizing the optical power coupled between the waveguide and the photodetector (PD), as even a small gap between them leads to optical mode loss at the interface. A co-planar in-fill idea is experimented by transfer printing the PD’s absorber region at the same height as silicon waveguide. To fill the gap, evaporated amorphous silicon (a-Si) with a refractive index of 3.1 in the telecom wavelength range is utilized. This strategy aims to achieve maximum coupling.
In transfer printing process, it is crucial to efficiently release the PD coupons along with smooth interface, for successful printing on target wafer. This work introduces for the first time, a combination of InGaAs and AlInAs as release layers for InP based devices yielding double the etch rate and almost isotropic etch compared to individual release layers (InGaAs or AlInAs). This facilitates direct bonding of the PD coupons to the target wafer since the interface roughness is extremely low as 0.2 nm over an area of 10 µm x 10 µm, contributing to high-speed of the PD. An excellent selectivity of 5410 is obtained with InP, which is 3.4 times higher than AlInAs and 7 times higher than InGaAs as release layers. These outcomes are accomplished at room
temperature thus saving time, cost, and energy for the entire process.
The above optimized processes are used in integration of high-speed InGaAs photodetector to SOI platform, by direct bonding, with 100 % yield. An ultra-thin 675 nm epitaxial stack is grown with dual release layer on InP substrate, where a PD of size 21 µm x 57 µm is fabricated. Such small dimension has the potential to fit 1 million devices on a 75 mm InP wafer. The same photodetectors are coupled to silicon waveguides via evanescent, grating and butt coupling mechanisms on the same target wafer. These PDs exhibit a maximum responsivity of 0.6 A/W, 47 nA dark current and with a data communication rate of 50 Gbps with on-off keying.
In future, this unique integration approach can be universally applied to any III-V active device like lasers and modulators to realise compact and high performance photonic integrated circuits.
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Keywords
Micro-transfer printing , Heterogeneous integration , High-speed photodetector , Coupling mechanism , InGaAs photodetector
Citation
Muthuganesan, H. 2024. Micro-transfer print integration of high-speed photodetectors to SOI platform. PhD Thesis, University College Cork.