Low-power SAR ADC for biomedical portable devices

Venkatesh, Madhan

Low-power SAR ADC for biomedical portable devices

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VenkateshM_PhD2024.pdf(50.29 MB)

Full Text E-thesis

Date

2024

Authors

Venkatesh, Madhan

Publisher

University College Cork

Abstract

In energy constrained edge devices such as wireless sensor nodes, Internet of Things (IoT) devices and biomedical implants, ultra-low power operation is a critical consideration when operating from a lifetime battery or an energy harvesting source. In such applications, it is important to ensure that all the sub-blocks are optimally powered, which means that each sub-block is provided with just enough energy to complete its task and no more. Successive-Approximation-Register (SAR) Analog to Digital Converters (ADCs) stand out as the preferred choice for such applications due to their remarkable energy efficiency and nearly digital architecture. The SAR architecture’s scalability allows for energy consumption optimisation across a broad spectrum of applications, ranging from a few kS/s for biomedical devices to a few MS/s for wireless communication. In SAR ADCs, the primary source of power dissipation is the comparator. Unlike other digital blocks such as control logic and DAC switching, the comparator’s energy consumption does not scale in the same manner with the supply voltage. Reducing power consumption in SAR ADCs with resolutions exceeding 10-bits poses challenges due to the power required in the comparator to meet stringent quantization noise specifications at low supply voltages. For medium resolutions (8-12 bits), the comparator typically constitutes 50%-60% of the ADC’s energy consumption. This thesis focuses on the design and implementation of a low-power embedded 14-bit SAR ADC on a 65nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The thesis introduces a switched-supply based comparator that reduces the effective supply voltage of the comparator during the decision phase without the requirement of a dedicated DC-DC down converter or an external supply rail. The proposed comparator achieves a 28% power consumption reduction when compared to the conventional designs. In addition, the design utilises a clock-boosting circuit instead of a bootstrapped switch on the input switch without degrading the achievable Signal-to-Noise-and-Distortion ratio (SNDR) and also achieves 46% reduction in power consumption compared to the bootstrapped switch. Synchronous low-power handcrafted logic is used to further reduce the power consumption. The 14-bit SAR ADC was fabricated in 65 nm CMOS and consumes 9.14 µW from a 1 V supply and achieves an SNDR of 71.7 dB at 0.5 MS/s resulting in a Walden Figure of Merit (FOM) of 5.7 fJ/Conv. This thesis also presents a programmable switched-supply comparator that uses a programmable reservoir capacitor to achieve a reduced effective supply voltage during the decision phase. This comparator achieves up to 50% power consumption reduction compared to a conventional dynamic comparator. Fabricated in 65nm CMOS, the silicon results of the PMOS-input programmable comparator show programmable power consumption and energy efficiency ranging from 2.7 - 4.1 µW and 0.22 - 0.5 pJ/conv, respectively. Similarly, the input-referred noise can be programmed from 100 - 180 µVrms. Additionally, the power (energy efficiency) and input-referred noise can be programmed at any clock cycle, making this design an ideal solution for a two-comparator SAR ADC architecture. In summary, this thesis presents design techniques focused on reducing the energy per conversion of SAR ADCs, with a primary emphasis on minimising energy during the comparison phase, making the developed design an excellent choice for IoT applications.

Keywords

SAR ADC , Switch supply comparator , Coarse and fine comparator , Clock boosting circuit , Custom MoM capacitor , Low power

Citation

Venkatesh, M. 2024. Low-power SAR ADC for biomedical portable devices. PhD Thesis, University College Cork.