Systematic modeling of electrostatics, transport, and statistical variability effects of interface traps in end-of-the-roadmap III–V MOSFETs

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dc.contributor.authorZagni, Nicolò
dc.contributor.authorCaruso, Enrico
dc.contributor.authorPuglisi, Francesco M.
dc.contributor.authorPavan, Paolo
dc.contributor.authorPalestri, Pierpaolo
dc.contributor.authorVerzellesi, Giovanni .
dc.contributor.funderSeventh Framework Programmeen
dc.date.accessioned2020-08-05T12:15:47Z
dc.date.available2020-08-05T12:15:47Z
dc.date.issued2020-03-03
dc.description.abstractThanks to their superior transport properties, indium gallium arsenide (InGaAs) metal-oxide-semiconductor field-effect transistors (MOSFETs) constitute an alternative to conventional silicon MOSFETs for digital applications at ultrascaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we: 1) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs dual-gate ultrathin body (DG-UTB) FETs and 2) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against multi-subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultrathin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This, in turn, implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.en
dc.description.statusPeer revieweden
dc.description.versionPublished Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationZagni, N., Caruso, E., Puglisi, F. M., Pavan, P., Palestri, P. and Verzellesi, G. (2020) 'Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs', IEEE Transactions on Electron Devices, 67(4), pp. 1560-1566. doi: 10.1109/TED.2020.2974966en
dc.identifier.doi10.1109/TED.2020.2974966en
dc.identifier.eissn1557-9646
dc.identifier.endpage1566en
dc.identifier.issn0018-9383
dc.identifier.issued4en
dc.identifier.journaltitleIEEE Transactions on Electron Devicesen
dc.identifier.startpage1560en
dc.identifier.urihttps://hdl.handle.net/10468/10355
dc.identifier.volume67en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.projectinfo:eu-repo/grantAgreement/EC/FP7::SP1::ICT/619326/EU/Technology CAD for III-V Semiconductor-based MOSFETs/III-V-MOSen
dc.rights© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.subjectIII–V metal–oxide–semiconductor field-effect transistors (MOSFETs)en
dc.subjectInterface trapsen
dc.subjectModelingen
dc.subjectScalingen
dc.subjectVariabilityen
dc.subjectIndium gallium arsenideen
dc.subjectElectrostaticsen
dc.subjectSolid modelingen
dc.subjectMOSFETen
dc.subjectIndium gallium arsenideen
dc.subjectElectrostaticsen
dc.subjectSolid modelingen
dc.subjectMOSFETen
dc.subjectElectron trapsen
dc.subjectLogic gatesen
dc.subjectSiliconen
dc.titleSystematic modeling of electrostatics, transport, and statistical variability effects of interface traps in end-of-the-roadmap III–V MOSFETsen
dc.typeArticle (peer-reviewed)en
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