Semiconductor nanowire fabrication by bottom-up and top-down paradigms

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dc.contributor.authorHobbs, Richard G.
dc.contributor.authorPetkov, Nikolay
dc.contributor.authorHolmes, Justin D.
dc.date.accessioned2016-03-01T12:46:46Z
dc.date.available2016-03-01T12:46:46Z
dc.date.issued2012-04-21
dc.date.updated2013-03-07T20:23:50Z
dc.description.abstractSemiconductor nanowires have been the subject of intensive research investment over the past few decades. Their physical properties afford them applications in a vast network of active microelectronic research fields, including logic device scaling in very large scale integrated circuits, sensor devices, and energy harvesting. A range of routes to semiconductor nanowire production have opened up as a result of advances in nanowire fabrication techniques over the last number of decades. These nanowire fabrication routes can usually be categorized into one of two paradigms, bottom-up or top-down. Microelectronic systems typically rely on integrated device platforms, where each device and component thereof can be individually addressed. This requirement for precise addressability places significant demands on the mode of fabrication, specifically with regard to device definition, placement and density, which have typically been strengths of top-down fabrication processes. However, in recent years, advances in bottom-up fabrication processes have opened up the possibility of a synergy between bottom-up and top-down processes to achieve the benefits of both. This review article highlights the important considerations required for the continued advancement of semiconductor nanowire fabrication with a focus on the application of semiconductor nanowire fabrication for next-generation field-effect transistor devices.en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationHOBBS, R. G., PETKOV, N. & HOLMES, J. D. 2012. Semiconductor Nanowire Fabrication by Bottom-Up and Top-Down Paradigms. Chemistry of Materials, 24, 1975-1991. http://dx.doi.org/10.1021/cm300570nen
dc.identifier.doi10.1021/cm300570n
dc.identifier.endpage1991en
dc.identifier.issn0897-4756
dc.identifier.issued11en
dc.identifier.journaltitleChemistry of Materialsen
dc.identifier.startpage1975en
dc.identifier.urihttps://hdl.handle.net/10468/2414
dc.identifier.volume24en
dc.language.isoenen
dc.publisherAmerican Chemical Societyen
dc.relation.urihttp://pubs.acs.org/journal/cmatex
dc.rights© 2012 American Chemical Society. This document is the Accepted Manuscript version of a Published Work that appeared in final form in Chemistry of Materials copyright © American Chemical Society after peer review and technical editing by the publisher. To access the final edited and published work see http://dx.doi.org/10.1021/cm300570nen
dc.subjectSemiconductorsen
dc.subjectNanowiresen
dc.subjectBottom-upen
dc.subjectTop-downen
dc.subjectFabricationen
dc.subjectDevice-scalingen
dc.subjectFabrication routesen
dc.subjectFabrication techniqueen
dc.subjectIntegrated deviceen
dc.subjectSemiconductor nanowireen
dc.subjectSensor deviceen
dc.subjectTop-down fabricationen
dc.subjectBottom-up fabricationen
dc.subjectVery large scale integrated circuiten
dc.subjectField effect transistorsen
dc.subjectLogic devicesen
dc.subjectMicroelectronicsen
dc.titleSemiconductor nanowire fabrication by bottom-up and top-down paradigmsen
dc.typeArticle (peer-reviewed)en
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