Low-temperature conductance oscillations in junctionless nanowire transistors
dc.contributor.author | Park, Jong-Tae | |
dc.contributor.author | Kim, Jin Young | |
dc.contributor.author | Lee, Chi-Woo | |
dc.contributor.author | Colinge, Jean-Pierre | |
dc.contributor.funder | Science Foundation Ireland | |
dc.contributor.funder | Incheon National University | |
dc.contributor.funder | Higher Education Authority | |
dc.date.accessioned | 2017-07-28T11:04:41Z | |
dc.date.available | 2017-07-28T11:04:41Z | |
dc.date.issued | 2010 | |
dc.description.abstract | Junctionless nanowire transistors show more marked oscillations conductance oscillations than inversion-mode devices. These oscillations can be observed at higher temperature, drain voltage, and gate voltage than in surface-channel, inversion-mode multigate metal-oxide-semiconductor field-effect devices. Clear oscillations are observed at 77 K at a drain voltage of 100 mV in devices with a 10 x 10 nm(2) cross section. (C) 2010 American Institute of Physics. (doi:10.1063/1.3506899) | en |
dc.description.sponsorship | Science Foundation Ireland (Grant No. 05/IN/I888: Advanced Scalable Silicon-on-Insulator Devices for Beyond-End-of-Roadmap Semiconductors.); Higher Education Authority (Programme for Research in Third-Level Institutions); University of Incheon (University of Incheon International Cooperative Research Grant 2010) | en |
dc.description.status | Peer reviewed | en |
dc.description.version | Published Version | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.articleid | 172101 | |
dc.identifier.citation | Park, J.-T., Kim, J. Y., Lee, C.-W. and Colinge, J.-P. (2010) 'Low-temperature conductance oscillations in junctionless nanowire transistors', Applied Physics Letters, 97(17), pp. 172101. doi: 10.1063/1.3506899 | en |
dc.identifier.doi | 10.1063/1.3506899 | |
dc.identifier.endpage | 2 | |
dc.identifier.issn | 0003-6951 | |
dc.identifier.issn | 1077-3118 | |
dc.identifier.issued | 17 | |
dc.identifier.journaltitle | Applied Physics Letters | en |
dc.identifier.startpage | 1 | |
dc.identifier.uri | https://hdl.handle.net/10468/4329 | |
dc.identifier.volume | 97 | |
dc.language.iso | en | en |
dc.publisher | AIP Publishing | en |
dc.relation.uri | http://aip.scitation.org/doi/abs/10.1063/1.3506899 | |
dc.rights | © 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Park, J.-T., Kim, J. Y., Lee, C.-W. and Colinge, J.-P. (2010) 'Low-temperature conductance oscillations in junctionless nanowire transistors', Applied Physics Letters, 97(17), pp. 172101 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3506899 | en |
dc.subject | Nanowires | en |
dc.subject | MOSFETs | en |
dc.subject | Doping | en |
dc.subject | Metal insulator semiconductor structures | en |
dc.subject | Temperature measurement | en |
dc.title | Low-temperature conductance oscillations in junctionless nanowire transistors | en |
dc.type | Article (peer-reviewed) | en |
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